From 99a0c4c3b561d074c178d71c0a392d565133b58a Mon Sep 17 00:00:00 2001
From: Krzysztof Parzyszek <kparzysz@codeaurora.org>
Date: Thu, 19 Oct 2017 16:59:22 +0000
Subject: [PATCH] [Hexagon] Fix store conversion from rr to io in optimize
 addressing modes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316170 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/Hexagon/HexagonOptAddrMode.cpp  | 11 +++++------
 test/CodeGen/Hexagon/addrmode-rr-to-io.mir | 22 ++++++++++++++++++++++
 2 files changed, 27 insertions(+), 6 deletions(-)
 create mode 100644 test/CodeGen/Hexagon/addrmode-rr-to-io.mir

diff --git a/lib/Target/Hexagon/HexagonOptAddrMode.cpp b/lib/Target/Hexagon/HexagonOptAddrMode.cpp
index dba6cdf3276..c7e5e55a6a7 100644
--- a/lib/Target/Hexagon/HexagonOptAddrMode.cpp
+++ b/lib/Target/Hexagon/HexagonOptAddrMode.cpp
@@ -361,7 +361,7 @@ bool HexagonOptAddrMode::changeLoad(MachineInstr *OldMI, MachineOperand ImmOp,
       Changed = false;
 
     DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n");
-    DEBUG(dbgs() << "[TO]: " << MIB << "\n");
+    DEBUG(dbgs() << "[TO]: " << *MIB << "\n");
   } else if (ImmOpNum == 2 && OldMI->getOperand(3).getImm() == 0) {
     short NewOpCode = HII->changeAddrMode_rr_io(*OldMI);
     assert(NewOpCode >= 0 && "Invalid New opcode\n");
@@ -372,7 +372,7 @@ bool HexagonOptAddrMode::changeLoad(MachineInstr *OldMI, MachineOperand ImmOp,
     OpStart = 4;
     Changed = true;
     DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n");
-    DEBUG(dbgs() << "[TO]: " << MIB << "\n");
+    DEBUG(dbgs() << "[TO]: " << *MIB << "\n");
   }
 
   if (Changed)
@@ -414,18 +414,17 @@ bool HexagonOptAddrMode::changeStore(MachineInstr *OldMI, MachineOperand ImmOp,
     }
     Changed = true;
     DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n");
-    DEBUG(dbgs() << "[TO]: " << MIB << "\n");
+    DEBUG(dbgs() << "[TO]: " << *MIB << "\n");
   } else if (ImmOpNum == 1 && OldMI->getOperand(2).getImm() == 0) {
     short NewOpCode = HII->changeAddrMode_rr_io(*OldMI);
     assert(NewOpCode >= 0 && "Invalid New opcode\n");
     MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
     MIB.add(OldMI->getOperand(0));
     MIB.add(ImmOp);
-    MIB.add(OldMI->getOperand(1));
-    OpStart = 2;
+    OpStart = 3;
     Changed = true;
     DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n");
-    DEBUG(dbgs() << "[TO]: " << MIB << "\n");
+    DEBUG(dbgs() << "[TO]: " << *MIB << "\n");
   }
   if (Changed)
     for (unsigned i = OpStart; i < OpEnd; ++i)
diff --git a/test/CodeGen/Hexagon/addrmode-rr-to-io.mir b/test/CodeGen/Hexagon/addrmode-rr-to-io.mir
new file mode 100644
index 00000000000..75eb0d38440
--- /dev/null
+++ b/test/CodeGen/Hexagon/addrmode-rr-to-io.mir
@@ -0,0 +1,22 @@
+# RUN: llc -march=hexagon -run-pass amode-opt %s -o - | FileCheck %s
+
+# This testcase used to crash.
+# CHECK: S2_storerb_io killed %r0, @var_i8, killed %r2
+
+--- |
+  define void @fred() { ret void }
+  @var_i8 = global [10 x i8] zeroinitializer, align 8
+...
+
+---
+name: fred
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: %r0
+      %r1 = A2_tfrsi @var_i8
+      %r2 = A2_tfrsi 255
+      S4_storerb_rr killed %r0, killed %r1, 0, killed %r2
+      PS_jmpret %r31, implicit-def %pc
+...
+
-- 
2.11.0