From 9abf0e829efe1d9537229af379a1f44807bdd868 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 10 May 2016 05:28:04 +0000 Subject: [PATCH] [X86][AVX512] Strengthen the assertions from r269001. We need VLX to use the 128/256-bit move opcodes for extended registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269019 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86InstrInfo.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index 4b507022868..45f3727a705 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -4653,7 +4653,7 @@ static unsigned getLoadStoreRegOpcode(unsigned Reg, return load ? (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) : (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr); } - assert(STI.hasAVX512() && "Using extended register requires AVX512"); + assert(STI.hasVLX() && "Using extended register requires VLX"); if (isStackAligned) return load ? X86::VMOVAPSZ128rm : X86::VMOVAPSZ128mr; else @@ -4669,13 +4669,14 @@ static unsigned getLoadStoreRegOpcode(unsigned Reg, else return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr; } - assert(STI.hasAVX512() && "Using extended register requires AVX512"); + assert(STI.hasVLX() && "Using extended register requires VLX"); if (isStackAligned) return load ? X86::VMOVAPSZ256rm : X86::VMOVAPSZ256mr; else return load ? X86::VMOVUPSZ256rm : X86::VMOVUPSZ256mr; case 64: assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass"); + assert(STI.hasVLX() && "Using 512-bit register requires AVX512"); if (isStackAligned) return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr; else -- 2.11.0