From 9ba154704ca74a88074c04a94a614a499b9da079 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Tue, 19 Sep 2017 14:02:16 +0000 Subject: [PATCH] [X86][SSE] Add 'redundant pand' test case from PR34620 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313632 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/X86/combine-and.ll | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/test/CodeGen/X86/combine-and.ll b/test/CodeGen/X86/combine-and.ll index f30fa61bbfb..5ce3f32cfd2 100644 --- a/test/CodeGen/X86/combine-and.ll +++ b/test/CodeGen/X86/combine-and.ll @@ -270,3 +270,22 @@ define <4 x i32> @ashr_mask7_v4i32(<4 x i32> %a0) { %2 = and <4 x i32> %1, ret <4 x i32> %2 } + +; +; SimplifyDemandedBits +; + +; PR34620 - redundant PAND after vector shift of a byte vector (PSRLW) +define <16 x i8> @PR34620(<16 x i8> %a0, <16 x i8> %a1) { +; CHECK-LABEL: PR34620: +; CHECK: # BB#0: +; CHECK-NEXT: psrlw $1, %xmm0 +; CHECK-NEXT: pand {{.*}}(%rip), %xmm0 +; CHECK-NEXT: pand {{.*}}(%rip), %xmm0 +; CHECK-NEXT: paddb %xmm1, %xmm0 +; CHECK-NEXT: retq + %1 = lshr <16 x i8> %a0, + %2 = and <16 x i8> %1, + %3 = add <16 x i8> %2, %a1 + ret <16 x i8> %3 +} -- 2.11.0