From 9da5c1013215176f2a4dbe7a804be899e12d5f68 Mon Sep 17 00:00:00 2001 From: buzbee Date: Fri, 28 Mar 2014 12:59:18 -0700 Subject: [PATCH] Quick compiler, MIPS resource cleanup MIPS architecture includes internal registers HI and LO. Similar to condition codes in other architectures, these internal resouces must be accounted for during instruction scheduling. Previously, the Quick backend for MIPS dealt with them by defining rHI and rLO pseudo registers - treating them as actual registers for def/use masks. This CL changes the handling of these resources to be in line with how condition codes are used elsewhere - leaving register definitions to be used for registers. Change-Id: Idcd77f3107b0c9b081ad05b1aab663fb9f41492d --- compiler/dex/compiler_enums.h | 6 +++++- compiler/dex/quick/mips/assemble_mips.cc | 10 +++++----- compiler/dex/quick/mips/int_mips.cc | 12 ++++++------ compiler/dex/quick/mips/mips_lir.h | 9 +++------ compiler/dex/quick/mips/target_mips.cc | 16 ++++++++++++++++ compiler/dex/quick/mir_to_lir.h | 4 ++++ compiler/dex/quick/x86/x86_lir.h | 4 ---- 7 files changed, 39 insertions(+), 22 deletions(-) diff --git a/compiler/dex/compiler_enums.h b/compiler/dex/compiler_enums.h index eb4a3367b..8ec1c18fc 100644 --- a/compiler/dex/compiler_enums.h +++ b/compiler/dex/compiler_enums.h @@ -401,7 +401,11 @@ enum OpFeatureFlags { kRegUseSP, kSetsCCodes, kUsesCCodes, - kUseFpStack + kUseFpStack, + kUseHi, + kUseLo, + kDefHi, + kDefLo }; enum SelectInstructionKind { diff --git a/compiler/dex/quick/mips/assemble_mips.cc b/compiler/dex/quick/mips/assemble_mips.cc index ee142e5d5..a5792549c 100644 --- a/compiler/dex/quick/mips/assemble_mips.cc +++ b/compiler/dex/quick/mips/assemble_mips.cc @@ -143,9 +143,9 @@ const MipsEncodingMap MipsMir2Lir::EncodingMap[kMipsLast] = { kFmtUnused, -1, -1, IS_BINARY_OP | IS_BRANCH | REG_USE01 | NEEDS_FIXUP, "bne", "!0r,!1r,!2t!0N", 8), ENCODING_MAP(kMipsDiv, 0x0000001a, - kFmtUnused, -1, -1, kFmtUnused, -1, -1, kFmtBitBlt, 25, 21, - kFmtBitBlt, 20, 16, IS_QUAD_OP | REG_DEF01 | REG_USE23, - "div", "!2r,!3r", 4), + kFmtBitBlt, 25, 21, kFmtBitBlt, 20, 16, kFmtUnused, -1, -1, + kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF_HI | REG_DEF_LO | REG_USE01, + "div", "!0r,!1r", 4), #if __mips_isa_rev >= 2 ENCODING_MAP(kMipsExt, 0x7c000000, kFmtBitBlt, 20, 16, kFmtBitBlt, 25, 21, kFmtBitBlt, 10, 6, @@ -198,11 +198,11 @@ const MipsEncodingMap MipsMir2Lir::EncodingMap[kMipsLast] = { "lw", "!0r,!1d(!2r)", 4), ENCODING_MAP(kMipsMfhi, 0x00000010, kFmtBitBlt, 15, 11, kFmtUnused, -1, -1, kFmtUnused, -1, -1, - kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, + kFmtUnused, -1, -1, IS_UNARY_OP | REG_DEF0 | REG_USE_HI, "mfhi", "!0r", 4), ENCODING_MAP(kMipsMflo, 0x00000012, kFmtBitBlt, 15, 11, kFmtUnused, -1, -1, kFmtUnused, -1, -1, - kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, + kFmtUnused, -1, -1, IS_UNARY_OP | REG_DEF0 | REG_USE_LO, "mflo", "!0r", 4), ENCODING_MAP(kMipsMove, 0x00000025, /* or using zero reg */ kFmtBitBlt, 15, 11, kFmtBitBlt, 25, 21, kFmtUnused, -1, -1, diff --git a/compiler/dex/quick/mips/int_mips.cc b/compiler/dex/quick/mips/int_mips.cc index dfe8b3527..b7940bb12 100644 --- a/compiler/dex/quick/mips/int_mips.cc +++ b/compiler/dex/quick/mips/int_mips.cc @@ -229,12 +229,12 @@ LIR* MipsMir2Lir::GenRegMemCheck(ConditionCode c_code, RegStorage reg1, RegStora RegLocation MipsMir2Lir::GenDivRem(RegLocation rl_dest, RegStorage reg1, RegStorage reg2, bool is_div) { - NewLIR4(kMipsDiv, rHI, rLO, reg1.GetReg(), reg2.GetReg()); + NewLIR2(kMipsDiv, reg1.GetReg(), reg2.GetReg()); RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); if (is_div) { - NewLIR2(kMipsMflo, rl_result.reg.GetReg(), rLO); + NewLIR1(kMipsMflo, rl_result.reg.GetReg()); } else { - NewLIR2(kMipsMfhi, rl_result.reg.GetReg(), rHI); + NewLIR1(kMipsMfhi, rl_result.reg.GetReg()); } return rl_result; } @@ -243,12 +243,12 @@ RegLocation MipsMir2Lir::GenDivRemLit(RegLocation rl_dest, RegStorage reg1, int bool is_div) { int t_reg = AllocTemp().GetReg(); NewLIR3(kMipsAddiu, t_reg, rZERO, lit); - NewLIR4(kMipsDiv, rHI, rLO, reg1.GetReg(), t_reg); + NewLIR2(kMipsDiv, reg1.GetReg(), t_reg); RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); if (is_div) { - NewLIR2(kMipsMflo, rl_result.reg.GetReg(), rLO); + NewLIR1(kMipsMflo, rl_result.reg.GetReg()); } else { - NewLIR2(kMipsMfhi, rl_result.reg.GetReg(), rHI); + NewLIR1(kMipsMfhi, rl_result.reg.GetReg()); } FreeTemp(t_reg); return rl_result; diff --git a/compiler/dex/quick/mips/mips_lir.h b/compiler/dex/quick/mips/mips_lir.h index 96cd3d8bb..c5150eec3 100644 --- a/compiler/dex/quick/mips/mips_lir.h +++ b/compiler/dex/quick/mips/mips_lir.h @@ -90,14 +90,12 @@ namespace art { #define MIPS_FP_REG_OFFSET 32 // Offset to distinguish DP FP regs. #define MIPS_FP_DOUBLE 64 -// Offset to distingish the extra regs. -#define MIPS_EXTRA_REG_OFFSET 128 // Reg types. #define MIPS_REGTYPE(x) (x & (MIPS_FP_REG_OFFSET | MIPS_FP_DOUBLE)) #define MIPS_FPREG(x) ((x & MIPS_FP_REG_OFFSET) == MIPS_FP_REG_OFFSET) -#define MIPS_EXTRAREG(x) ((x & MIPS_EXTRA_REG_OFFSET) == MIPS_EXTRA_REG_OFFSET) #define MIPS_DOUBLEREG(x) ((x & MIPS_FP_DOUBLE) == MIPS_FP_DOUBLE) #define MIPS_SINGLEREG(x) (MIPS_FPREG(x) && !MIPS_DOUBLEREG(x)) +// FIXME: out of date comment. /* * Note: the low register of a floating point pair is sufficient to * create the name of a double, but require both names to be passed to @@ -157,6 +155,8 @@ enum MipsResourceEncodingPos { #define ENCODE_MIPS_REG_SP (1ULL << kMipsRegSP) #define ENCODE_MIPS_REG_LR (1ULL << kMipsRegLR) #define ENCODE_MIPS_REG_PC (1ULL << kMipsRegPC) +#define ENCODE_MIPS_REG_HI (1ULL << kMipsRegHI) +#define ENCODE_MIPS_REG_LO (1ULL << kMipsRegLO) enum MipsNativeRegisterPool { rZERO = 0, @@ -248,9 +248,6 @@ enum MipsNativeRegisterPool { rDF14 = rF28 + MIPS_FP_DOUBLE, rDF15 = rF30 + MIPS_FP_DOUBLE, #endif - rHI = MIPS_EXTRA_REG_OFFSET, - rLO, - rPC, }; const RegStorage rs_rZERO(RegStorage::k32BitSolo, rZERO); diff --git a/compiler/dex/quick/mips/target_mips.cc b/compiler/dex/quick/mips/target_mips.cc index 67a44fa74..f15a40804 100644 --- a/compiler/dex/quick/mips/target_mips.cc +++ b/compiler/dex/quick/mips/target_mips.cc @@ -151,6 +151,22 @@ void MipsMir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags) { if (flags & REG_DEF_LR) { lir->u.m.def_mask |= ENCODE_MIPS_REG_LR; } + + if (flags & REG_DEF_HI) { + lir->u.m.def_mask |= ENCODE_MIPS_REG_HI; + } + + if (flags & REG_DEF_LO) { + lir->u.m.def_mask |= ENCODE_MIPS_REG_LO; + } + + if (flags & REG_USE_HI) { + lir->u.m.use_mask |= ENCODE_MIPS_REG_HI; + } + + if (flags & REG_USE_LO) { + lir->u.m.use_mask |= ENCODE_MIPS_REG_LO; + } } /* For dumping instructions */ diff --git a/compiler/dex/quick/mir_to_lir.h b/compiler/dex/quick/mir_to_lir.h index bac35aad6..c8ea25bd8 100644 --- a/compiler/dex/quick/mir_to_lir.h +++ b/compiler/dex/quick/mir_to_lir.h @@ -84,6 +84,10 @@ typedef uint32_t CodeOffset; // Native code offset in bytes. #define SETS_CCODES (1ULL << kSetsCCodes) #define USES_CCODES (1ULL << kUsesCCodes) #define USE_FP_STACK (1ULL << kUseFpStack) +#define REG_USE_LO (1ULL << kUseLo) +#define REG_USE_HI (1ULL << kUseHi) +#define REG_DEF_LO (1ULL << kDefLo) +#define REG_DEF_HI (1ULL << kDefHi) // Common combo register usage patterns. #define REG_DEF01 (REG_DEF0 | REG_DEF1) diff --git a/compiler/dex/quick/x86/x86_lir.h b/compiler/dex/quick/x86/x86_lir.h index 797bc8260..1759cbefb 100644 --- a/compiler/dex/quick/x86/x86_lir.h +++ b/compiler/dex/quick/x86/x86_lir.h @@ -106,12 +106,9 @@ namespace art { #define X86_FP_REG_OFFSET 32 // Offset to distinguish DP FP regs. #define X86_FP_DOUBLE (X86_FP_REG_OFFSET + 16) -// Offset to distingish the extra regs. -#define X86_EXTRA_REG_OFFSET (X86_FP_DOUBLE + 16) // Reg types. #define X86_REGTYPE(x) (x & (X86_FP_REG_OFFSET | X86_FP_DOUBLE)) #define X86_FPREG(x) ((x & X86_FP_REG_OFFSET) == X86_FP_REG_OFFSET) -#define X86_EXTRAREG(x) ((x & X86_EXTRA_REG_OFFSET) == X86_EXTRA_REG_OFFSET) #define X86_DOUBLEREG(x) ((x & X86_FP_DOUBLE) == X86_FP_DOUBLE) #define X86_SINGLEREG(x) (X86_FPREG(x) && !X86_DOUBLEREG(x)) @@ -135,7 +132,6 @@ enum X86ResourceEncodingPos { kX86RegEnd = kX86FPStack, }; -#define ENCODE_X86_REG_LIST(N) (static_cast(N)) #define ENCODE_X86_REG_SP (1ULL << kX86RegSP) #define ENCODE_X86_FP_STACK (1ULL << kX86FPStack) -- 2.11.0