From 9e56e4c985c3fca7e3f4ff20a202e18a50b0430e Mon Sep 17 00:00:00 2001 From: brolley Date: Fri, 24 Jun 2005 18:37:26 +0000 Subject: [PATCH] New testsuite --- .../testsuite/sidcomp.cgen-cpu.ms1/ChangeLog | 88 +++++++++++ .../testsuite/sidcomp.cgen-cpu.ms1/addinsns.s | 43 ++++++ .../testsuite/sidcomp.cgen-cpu.ms1/ctinsns.s | 70 +++++++++ .../testsuite/sidcomp.cgen-cpu.ms1/intctrlinsns.s | 21 +++ .../testsuite/sidcomp.cgen-cpu.ms1/ioinsns.s | 27 ++++ .../testsuite/sidcomp.cgen-cpu.ms1/logicalinsns.s | 72 +++++++++ .../testsuite/sidcomp.cgen-cpu.ms1/memoryinsns.s | 170 +++++++++++++++++++++ .../testsuite/sidcomp.cgen-cpu.ms1/ms1-allinsn.exp | 18 +++ .../sidcomp.cgen-cpu.ms1/ms1-state-snapshot.exp | 127 +++++++++++++++ .../testsuite/sidcomp.cgen-cpu.ms1/mulinsns.s | 63 ++++++++ .../testsuite/sidcomp.cgen-cpu.ms1/shiftinsns.s | 83 ++++++++++ .../testsuite/sidcomp.cgen-cpu.ms1/subinsns.s | 62 ++++++++ .../testsuite/sidcomp.cgen-cpu.ms1/test-img.x | Bin 0 -> 14360 bytes .../testsuite/sidcomp.cgen-cpu.ms1/testutils.inc | 129 ++++++++++++++++ 14 files changed, 973 insertions(+) create mode 100644 sid/component/testsuite/sidcomp.cgen-cpu.ms1/ChangeLog create mode 100644 sid/component/testsuite/sidcomp.cgen-cpu.ms1/addinsns.s create mode 100644 sid/component/testsuite/sidcomp.cgen-cpu.ms1/ctinsns.s create mode 100644 sid/component/testsuite/sidcomp.cgen-cpu.ms1/intctrlinsns.s create mode 100644 sid/component/testsuite/sidcomp.cgen-cpu.ms1/ioinsns.s create mode 100644 sid/component/testsuite/sidcomp.cgen-cpu.ms1/logicalinsns.s create mode 100644 sid/component/testsuite/sidcomp.cgen-cpu.ms1/memoryinsns.s create mode 100644 sid/component/testsuite/sidcomp.cgen-cpu.ms1/ms1-allinsn.exp create mode 100644 sid/component/testsuite/sidcomp.cgen-cpu.ms1/ms1-state-snapshot.exp create mode 100644 sid/component/testsuite/sidcomp.cgen-cpu.ms1/mulinsns.s create mode 100644 sid/component/testsuite/sidcomp.cgen-cpu.ms1/shiftinsns.s create mode 100644 sid/component/testsuite/sidcomp.cgen-cpu.ms1/subinsns.s create mode 100755 sid/component/testsuite/sidcomp.cgen-cpu.ms1/test-img.x create mode 100644 sid/component/testsuite/sidcomp.cgen-cpu.ms1/testutils.inc diff --git a/sid/component/testsuite/sidcomp.cgen-cpu.ms1/ChangeLog b/sid/component/testsuite/sidcomp.cgen-cpu.ms1/ChangeLog new file mode 100644 index 0000000000..49c838b835 --- /dev/null +++ b/sid/component/testsuite/sidcomp.cgen-cpu.ms1/ChangeLog @@ -0,0 +1,88 @@ +2001-09-17 Ben Elliston + + * ms1-state-snapshot.exp: Run if $sidtarget(ms1) is set. + +2001-08-23 graydon hoare + + * ms1-state-snapshot.exp: New test. + * test-img.x: New binary file for test. + +2001-08-02 John Healy + + * ms1-allinsn.exp: Load of basic-sid and run tests + using run-sid-tests-raw. + +2001-05-22 John Healy + + * addinsns.s, ctinsn.s, intctrlinsns.s, ioinsns.s, logicalinsns.s, + memoryinsns.s, memoryinsns.s, mulinsns.s, shiftinsns.s, subinsns.s: + Added machine identification. + * ms1-allinsn.exp: Added --nosched to assembler flags. + +2001-05-17 John Healy + + * ioinsns.s: Added tests for the rest of the io instructions. + +2001-05-14 John Healy + + * ctinsns.s: Added test for brne instruction. + +2001-04-12 John Healy + + * ctinsns.s: Updated expected value for pc offset from jal insn. + +2001-04-11 John Healy + + * testutils.inc: Modified macros to use gloss-based syscalls and + to respect scheduling restrictions. + * addinsns.s, intctrlinsns.s, logicalinsns.s, memoryinsns.s, + mulinsns.s, shiftinsns.s, subinsns.s: Added .align directives to + .data sections and added nop's where necessary to obey the rules + of scheduling restrictions. + +2001-04-09 John Healy + + * ctinsns.s: Adjusted test cases to test for delayed branching. + * testutils.inc: Modified macros to allow for delayed branching. + +2001-04-09 John Healy + + * mulinsns.s: Added more tests. + +2001-04-06 John Healy + + * ctinsns.s, intctrlinsns.s, ioinsns.s, logicalinsns.s + memoryinsns.s, mulinsns.s shiftinsns.s, subinsns.s: Renamed to have + better filename extension (.cgs changed to .s). New tests also added + to each file. + * addinsns.s: New file. Tests from add.cgs, addi.cgs and addui.cgs + grouped into addinsns.s. + * testutils.inc: Improved assertion and loading macros. + +2001-04-05 John Healy + + * intctrlinsns.cgs: New tests added. + +2001-04-03 John Healy + + * add.cgs: Improved tests. + * addi.cgs: New file. + * addiinsns.cgs: New file. + * addui.cgs: New file. + * ctinsns.cgs: New file. + * intctrlinsns.cgs: New file. + * ioinsns.cgs: New file. + * logicalinsns.cgs: New file. + * memoryinsns.cgs: New file. + * mulinsns.cgs: New file. + * shiftinsns.cgs: New file. + * subinsns.cgs: New file. + * testutils.inc: New file. + +2001-03-28 John Healy + + * sidcomp.cgen-cpu.ms1/testutils.inc: Added support for + syscalls with up to three arguments. + * sidcomp.cgen-cpu.ms1/allinsn.exp: New file. + * sidcomp.cgen-cpu.ms1/add.cgs: New file. + diff --git a/sid/component/testsuite/sidcomp.cgen-cpu.ms1/addinsns.s b/sid/component/testsuite/sidcomp.cgen-cpu.ms1/addinsns.s new file mode 100644 index 0000000000..e5e53c446a --- /dev/null +++ b/sid/component/testsuite/sidcomp.cgen-cpu.ms1/addinsns.s @@ -0,0 +1,43 @@ +# mach(): ms1 + + .include "testutils.inc" + start + + loadwl R7, value1 + loadwl R8, value2 + +testadd: + add R9, R7, R8 + assertv R9, $1235 + +testaddi: + addi R9, R8, #1 ; Positive immediate value + assertv R9, $1235 + +testaddiagain: + addi R9, R9, #-1 + assertv R9, $1234 + +testaddionemoretime: + loadwl R7, value1 ; R7 contains 1. + addui R9, R0, #0 ; Clear R9: R9 contains 0. + addi R9, R0, #-3 ; Put expected result in R9. + addi R7, R7, #-4 ; R7 = R7 + -4 = -3 + assertv R7,-3 + +testaddui: + addui R9, R8, #1 + assertv R9, $1235 + +testadduiagain: + loadval R7, -6 + addui R9, R7, #1 + assertv R9, -5 + +pass: + pass + + .data + .align 4 +value1: .word 0x1 +value2: .word 0x1234 diff --git a/sid/component/testsuite/sidcomp.cgen-cpu.ms1/ctinsns.s b/sid/component/testsuite/sidcomp.cgen-cpu.ms1/ctinsns.s new file mode 100644 index 0000000000..c5628880f5 --- /dev/null +++ b/sid/component/testsuite/sidcomp.cgen-cpu.ms1/ctinsns.s @@ -0,0 +1,70 @@ +# mach(): ms1 + + .include "testutils.inc" + start + + loadwl R1, value1 + loadwl R2, value2 + +testbrlt: + assertv R14, 0 + brlt R1, R2, testbrle + addi R14, R0, #1 + +testbrle: + assertv R14, 1 + brle R1,R2, testbrle2 + addi R14, R14, #1 + +testbrle2: + assertv R14, 2 + brle R1, R1, testbreq + addi R14, R14, #1 + +testbreq: + assertv R14, 3 + breq R1, R1, testjmp + addi R14, R14, #1 + +testjmp: + assertv R14, 4 + jmp testjal + addi R14, R14, #1 + +testjal: + assertv R14, 5 + loadval R2, nobranchbrle + nop + +jallbl: jal R3, R2 + addi R14, R14, #1 + +nobranchbrle: + assertv R14, 6 + assertv R3, (jallbl + 8) ; Did jal store the right return address? + brle R2, R1, fail + nop + +nobranchbrlt: + brlt R2, R1, fail + nop + +nobranchbreq: + breq R2, R1, fail + nop + +brne: + brne R0,R3,pass + nop + fail + +pass: + pass + +fail: + fail + + .data + .align 4 +value1: .word 0001 +value2: .word 0x1234 diff --git a/sid/component/testsuite/sidcomp.cgen-cpu.ms1/intctrlinsns.s b/sid/component/testsuite/sidcomp.cgen-cpu.ms1/intctrlinsns.s new file mode 100644 index 0000000000..c9f832aea8 --- /dev/null +++ b/sid/component/testsuite/sidcomp.cgen-cpu.ms1/intctrlinsns.s @@ -0,0 +1,21 @@ +# mach(): ms1 + + .include "testutils.inc" + start + + ; Interrupts should be disabled at startup. + si R4; Should issue error message. + ei + addi R1, R0, #75 + si R4; Should be ok. + ei + di + si R4; Should issue error message. + loadval R6,pass + reti R6 + add R0, R0, R0 + fail + +pass: + pass + diff --git a/sid/component/testsuite/sidcomp.cgen-cpu.ms1/ioinsns.s b/sid/component/testsuite/sidcomp.cgen-cpu.ms1/ioinsns.s new file mode 100644 index 0000000000..da082c0cfe --- /dev/null +++ b/sid/component/testsuite/sidcomp.cgen-cpu.ms1/ioinsns.s @@ -0,0 +1,27 @@ +# mach(): ms1 + + .include "testutils.inc" + start + + loadwl R1, value1 + loadwl R2, value2 + loadwl R3, value3 + + outb R1, #0, R2 + outh R2, #0, R2 + outw R3, #0, R2 + inb R1, R1, #0 + assertv R1, 0 + inh R2, R2, #0 + assertv R2, 0 + inw R3, R3, #0 + assertv R3, 0 + +pass: + pass + + .data + .align 4 +value1: .word 0001 +value2: .word 0x1234 +value3: .word 0x5678 diff --git a/sid/component/testsuite/sidcomp.cgen-cpu.ms1/logicalinsns.s b/sid/component/testsuite/sidcomp.cgen-cpu.ms1/logicalinsns.s new file mode 100644 index 0000000000..6bae01a2ad --- /dev/null +++ b/sid/component/testsuite/sidcomp.cgen-cpu.ms1/logicalinsns.s @@ -0,0 +1,72 @@ +# mach(): ms1 + + .include "testutils.inc" + start + + loadval R6, value2 ; Use this throughout. To get at value1 or value2, + ; just use +/-1 offset. No need to waste another reg. + + loadval R7, 0xffff ; To be used as a mask value throughout. + loadval R8, 0x0 ; To be used as a mask value throughout. + ldw R9, R6, #0 ; R9 should contain 0xf0f0f0f0 for use throughout. + +testand: + and R10, R9, R7 + assertv R10, 0xf0f0 + +testandi: + andi R10, R9, #$ffff + assertv R10, 0x0000f0f0 + +testor: + or R10, R9, R7 + assertv R10, 0xf0f0ffff + +testori: + ori R10, R9, #$ffff + assertv R10, 0xf0f0ffff + +testxor: + xor R10, R9, R7 + assertv R10, 0xf0f00f0f + +testxori: + xori R10, R9, #$ffff + assertv R10, 0xf0f00f0f + +testnand: + nand R10, R9, R7 + assertv R10, 0xffff0f0f + +testnandi: + nandi R10, R9, #$ffff + assertv R10, 0xffff0f0f + +testnor: + nor R10, R9, R7 + ;assertv R10, 0x0f0f0000 + +testnori: + nori R10, R9, #$ffff + assertv R10, 0x0f0f0000 + +testxnor: + xnor R10, R9, R7 + assertv R10, 0x0f0ff0f0 + +testxnori: + xnori R10, R9, #$ffff + assertv R10, 0x0f0ff0f0 + +testldui: + ldui R10,#$beef + assertv R10, 0xbeef0000 + +pass: + pass + + + .data + .align 4 +value1: .word 0x1 +value2: .word 0xf0f0f0f0 diff --git a/sid/component/testsuite/sidcomp.cgen-cpu.ms1/memoryinsns.s b/sid/component/testsuite/sidcomp.cgen-cpu.ms1/memoryinsns.s new file mode 100644 index 0000000000..cb3752b8f7 --- /dev/null +++ b/sid/component/testsuite/sidcomp.cgen-cpu.ms1/memoryinsns.s @@ -0,0 +1,170 @@ +# mach(): ms1 + + .include "testutils.inc" + start + + ; Test ldw with 0 offset. +test1: + loadval R7, value1 + ldw R8, R7, #0 + assertv R8, 0x1234 + +test2: + loadval R7, value2 + ldw R8, R7, #0 + assertv R8, 0x12345678 + +test3: + loadval R7, value3 + ldw R8, R7, #0; + assertv R8, 0xbeef0000 + + ; Test ldw with non-zero offsets. +test4: + loadval R7, value1 + ldw R8, R7, #4 + assertv R8, 0x12345678 + +test5: + loadval R7, value3 + ldw R8, R7, #-4 + assertv R8, 0x12345678 + + ; test stw with 0 offset +test6: + loadval R7, value2 ; Where we want to store the new value. + loadval R8, $87654321 ; The new value: 0x87654321 + stw R8, R7, #0 ; Use stw to fetch the word + loadwl R9, value2 ; Load it into R9 as well. + assertr R8, R9 ; Make sure they're equal. + +test7: + loadval R7, value1 + loadval R8, $4321 + stw R8, R7, #0 + loadwl R9, value1 + assertr R8, R9 + +test8: + loadval R7, value3 + loadval R8, $feed + stw R8, R7, #0 + loadwl R9, value3 + assertr R8, R9 + + ; test stw with non-zero offset +test9: + loadval R7, value1 + loadval R8, $deadbeef + stw R8, R7, #4 + loadwl R9, value2 + assertr R8, R9 + +test10: + loadval R7, value2 + loadval R8, $deadbeef + stw R8, R7, #-4 + loadwl R9, value1 + assertr R8, R9 + +;; The ldb, ldbu and stb instructions are not really part of the +;; mRISC-I architecture. They're part of the mRISC-II, but since +;; the compiler has switches to generate/not generate them (in +;; support of the future mRISC-II chip), we'll implement and +;; test them so that the compiler developer can use them to +;; test his code generation. + +test11: + loadval R7, value5 + ldb R8, R7, #0 ; 0xffffffde (0xde sign extd) should be in R8. + assertv R8, 0xffffffde + +test12: + loadval R7, value6 + ldb R8, R7, #-1 + assertv R8, 0xffffffde + +test13: + loadval R7, value5 + ldbu R8, R7, #0 ; 0xffffffde (0xde sign extd) should be in R8. + assertv R8, 0xde + +test14: + loadval R7, value6 + ldbu R8, R7, #-1 ; 0xffffffde (0xde sign extd) should be in R8. + assertv R8, 0xde + +test15: + loadval R7, value5 ; Where we want to store the new value. + loadval R8, $fa ; The new value: 0xfa + stb R8, R7, #0 ; Store the new byte at value5 + ldbu R9, R7,#0 ; Put the new byte into R9 + assertr R8, R9 ; Make sure they're equal. + +test16: + loadval R7, value7 ; Where we want to store the new value. + loadval R8, $ce ; The new value: 0xce + stb R8, R7, #-1 ; Put the new byte at value6 + loadval R9, value6 ; Get value 6 into R9 + ldbu R10, R9,#0 ; Read the byte at value6 into R10 + assertr R8, R10 ; Make sure they're equal. + +;; ldw and stw are for word access and ignore the two low-order bits so that they +;; will only read a word from word-aligned addresses. Therefore, if addr1 is +;; word-alligned, reading from/writing to addr1+[0,1,2,3] should produce the +;; same results. The follow two tests check this behaviour. + +test17: + ; These should all load the same word. + loadval R7, value0 + ldw R8, R7, #0 ; Load word at value0 into R8. + assertv R8, 0xaceface + + ldw R8, R7, #1 ; Load word at value0 + 1 into R8. + assertv R8, 0xaceface + + ldw R8, R7, #2 ; Load word at value0 + 2 into R8. + assertv R8, 0xaceface + + ldw R8, R7, #3 ; Load word at value0 + 3 into R8. + assertv R8, 0xaceface + +test18: + ; These should all write to the same location. + loadval R7, value0 + loadval R8, 0xfeedbeef + stw R8, R7, #0 + loadwl R9, value0 + assertv R9, 0xfeedbeef + + loadval R8, 0xbadbed ; Change the value to be written to location value0 + stw R8, R7, #1 ; Write to address value0 + 1. + loadwl R9, value0 ; Load word at value0 into R9. + assertv R9, 0xbadbed ; Make sure it's the same as the new value. + + loadval R8, 0xfeedcab ; Change the value to be written to location value0 + stw R8, R7, #2 ; Write to address value0 + 2. + loadwl R9, value0 ; Load word at address value0 into R9. + assertv R9, 0xfeedcab + + loadval R8, 0xabcdef1 ; Change the value to be written to location value0 + stw R8, R7, #2 ; Write to address value0 + 3. + loadwl R9, value0 ; Load word at address value0 into R9. + assertv R9, 0xabcdef1 + +pass: + pass + + .data + .align 4 +value0: .word 0xaceface +value1: .word 0x1234 +value2: .word 0x12345678 + .align 1 +value3: .byte 0xbe +value4: .byte 0xef + .org 0x100 + .align 1 +value5: .byte 0xde +value6: .byte 0xed +value7: .byte 0xaa diff --git a/sid/component/testsuite/sidcomp.cgen-cpu.ms1/ms1-allinsn.exp b/sid/component/testsuite/sidcomp.cgen-cpu.ms1/ms1-allinsn.exp new file mode 100644 index 0000000000..70f60e363e --- /dev/null +++ b/sid/component/testsuite/sidcomp.cgen-cpu.ms1/ms1-allinsn.exp @@ -0,0 +1,18 @@ +# mRISC-I simulator testsuite. + +if {! $sidtarget(ms1)} { untested "hw-cpu-ms1 not available"; return } + +# Load a baseboard description for SID simulators. +load_base_board_description "basic-sid" + +# load support procs (none yet) +load_lib "cpudefs.exp" + +# all machines +set all_machs "ms1" + +# Add --nosched to the flags to supress scheduling restrictions. +set gas_flags "--gdwarf2 --nosched" + +# Run the tests +run-sid-tests-raw ms1-elf ms1 $srcdir/sidcomp.cgen-cpu.ms1 "*.s" $gas_flags "" "" ms1-gloss.conf x diff --git a/sid/component/testsuite/sidcomp.cgen-cpu.ms1/ms1-state-snapshot.exp b/sid/component/testsuite/sidcomp.cgen-cpu.ms1/ms1-state-snapshot.exp new file mode 100644 index 0000000000..0ae4eec31e --- /dev/null +++ b/sid/component/testsuite/sidcomp.cgen-cpu.ms1/ms1-state-snapshot.exp @@ -0,0 +1,127 @@ +# Testsuite for the CPU state snapshot and restoring. +# Copyright (C) 2001 Red Hat + +if {! $sidtarget(ms1)} { untested "hw-cpu-ms1 not available"; return } + +set cpu "ms1" +set filename "$srcdir/sidcomp.cgen-cpu.ms1/test-img.x" +set conf_file "statesnap.conf" +set start_insn 0x22d4 + + +set test "sid configuration" +sid_config_component_etc_test_with_tracing "$conf_file" \ + "load libcgencpu.la cgen_component_library" \ + "hw-cpu-$cpu" \ + "load libmemory.la mem_component_library +load libloader.la loader_component_library + +new hw-memory-ram/rom-basic mem +new sw-load-elf loader + +set loader file $filename +connect-pin loader start-pc-set -> real-victim start-pc-set! +connect-pin loader endian-set -> real-victim endian-set! +connect-bus loader load-accessor-insn mem read-write-port +connect-bus loader load-accessor-data mem read-write-port + +set mem size 0xffffff +connect-bus real-victim data-memory mem read-write-port +connect-bus real-victim insn-memory mem read-write-port + +relate tester loader loader +" +pass $test + + +set test "sid startup" +if [sid_start "$conf_file"] then { pass $test } else { fail $test ; return } + + +set test "acquire loader load! pin" +set load_pin [sid_cmd "sid::component::find_pin [sid_cmd {set relationships(loader)}] load!"] +if {$load_pin != ""} { pass $test } else { fail $test } + +set test "acquire cpu reset! pin" +set reset_pin [sid_cmd "sid::component::find_pin $victim reset!"] +if {$reset_pin == ""} then { fail $test } else { pass $test } + +set test "acquire cpu step! pin" +set step_pin [sid_cmd "sid::component::find_pin $victim step!"] +if {$step_pin == ""} then { fail $test } else { pass $test } + +set test "acquire cpu start-pc-set! pin" +set set_pc_pin [sid_cmd "sid::component::find_pin $victim start-pc-set!"] +if {$set_pc_pin == ""} then { fail $test } else { pass $test } + +sid_cmd "sid::pin::driven_h4 $reset_pin 1" +sid_cmd "sid::pin::driven_h4 $load_pin 1" + +# ignore any initialization in crt0; we're just doing simple memory writes +set test "advancing to interesting position of test image" +sid_cmd "sid::pin::driven_h4 $set_pc_pin $start_insn" +set result [sid_cmd "sid::component::attribute_value $victim pc"] +if {$result != $start_insn} then { fail $test } else { pass $test } + + +# set our step-size to 100, to finish test quickly +set test "set step-insn-count attribute" +set result [sid_cmd "sid::component::set_attribute_value $victim step-insn-count 100"] +if {$result == ""} then { fail $test } else { pass $test } + +# advance 100 insns into interesting stuff +sid_cmd "sid::pin::driven_h4 $step_pin 1" + +# save state 1's PC +set test "storing state 1's pc value" +set first_pc [sid_cmd "sid::component::attribute_value $victim pc"] +if {$first_pc == "" } then { fail $test } else { pass $test } + + +# capture state +set test "snapshot initial CPU state" +set first_state [sid_cmd "sid::component::attribute_value $victim state-snapshot"] +if {$first_state == ""} then { fail $test } else { pass $test } + + +# advance through 100 more insns +sid_cmd "sid::pin::driven_h4 $step_pin 1" + + +# capture state +set test "snapshot final CPU state" +set second_state [sid_cmd "sid::component::attribute_value $victim state-snapshot"] +if {$second_state == ""} then { fail $test } else { pass $test } + + +# rewind to first capture +set test "restore initial CPU state" +set result [sid_cmd "sid::component::set_attribute_value $victim state-snapshot \"$first_state\""] +if {$result == ""} then { fail $test } else { pass $test } + + +# check that pc was reset +set test "checking pc value rewound properly" +set rewind_pc [sid_cmd "sid::component::attribute_value $victim pc"] +if {$rewind_pc != $first_pc } then { fail $test } else { pass $test } + + +# advance through second 100 insns again +sid_cmd "sid::pin::driven_h4 $step_pin 1" + +# capture state +set test "snapshot final CPU state again" +set third_state [sid_cmd "sid::component::attribute_value $victim state-snapshot"] +if {$third_state == ""} then { fail $test } else { pass $test } + +# compare states +set test "comparing second and third states" +if {$second_state != $third_state} then { fail $test } else { pass $test } + + +set test "sid stop" +if {[sid_stop]} { pass $test } else { fail $test ; return } + +# zap temp file if tests were successful +global exit_status +if {$exit_status == "0"} { file delete "$conf_file" } diff --git a/sid/component/testsuite/sidcomp.cgen-cpu.ms1/mulinsns.s b/sid/component/testsuite/sidcomp.cgen-cpu.ms1/mulinsns.s new file mode 100644 index 0000000000..167ede129c --- /dev/null +++ b/sid/component/testsuite/sidcomp.cgen-cpu.ms1/mulinsns.s @@ -0,0 +1,63 @@ +# mach(): ms1 + + .include "testutils.inc" + start + +test1: ; mul: + loadval R6, 0xfff + loadval R7, 0xfff + mul R8,R7,R6 + assertv R8, 0xffe001 + +test2: + ; mul: -1*1 = +1 + loadval R6, 0x1 + loadval R7, -1 + mul R8,R7,R6 + assertv R8, -1 + +test3: + ; mul: -1*-1 = 1 + loadval R6, -1 + loadval R7, -1 + mul R8,R7,R6 + assertv R8, 1 + +test4: + ; mul: 0x7fff * 0x7fff = 0x3fff0001 + loadval R6, 0x7fff + loadval R7, 0x7fff + mul R8,R7,R6 + assertv R8, 0x3fff0001 + + +test5: ; muli + loadval R6, 0xfff + muli R8,R6,#$fff + assertv R8, 0xffe001 + +test6: + ; muli: -1*-1 = +1 + loadval R6, -1 + muli R8,R6, #-1 + assertv R8, 1 + +test7: + ; muli: -1*1 = -1 + loadval R6, 1 + muli R8,R6,#-1 + assertv R8, -1 + +test8: + ; muli: 0x7fff * 0x7fff = 0x3fff0001 + loadval R6, 0x7fff + muli R8,R7,#$7fff + assertv R8, 0x3fff0001 + + pass + + .data + .align 4 +value1: + .word 0xffff + diff --git a/sid/component/testsuite/sidcomp.cgen-cpu.ms1/shiftinsns.s b/sid/component/testsuite/sidcomp.cgen-cpu.ms1/shiftinsns.s new file mode 100644 index 0000000000..b8cb3e81b2 --- /dev/null +++ b/sid/component/testsuite/sidcomp.cgen-cpu.ms1/shiftinsns.s @@ -0,0 +1,83 @@ +# mach(): ms1 + + .INCLUDE "testutils.inc" + start + + loadwl R7 value2 ; Load 0x0f0f0f0f into R7 + addui R8, R0, #4 ; Load the value we want to shift by (4) into R8. + +test1: + ; Test lsl - basic test. + lsl R7, R7, R8 ; Shift left by 4 bits: R7 should be 0xf0f0f0f0. + + ; Put the expected result into R9. + loadwl R9, value3 + + ; Check to see if it's correct. + assertr R9,R7 + +test2: + ; Test lsr - basic test. + lsr R7, R7, R8 ; Shift right by 4 bits: R7 should be 0x0f0f0f0f. + + ; Put the expected value in R9 + loadwl R9, value2 + + ; Check to see if it's correct. + assertr R9,R7 + +test3: + ; Test lsli - basic test. + lsli R7, R7, #4 ; Shift left by 4 bits: R7 should be 0xf0f0f0f0. + + ; Put the expected result into R9. + loadwl R9, value3 + + ; Check to see if it's correct. + assertr R9,R7 + +test4: + ; Test lsri - basic test. + lsri R7, R7, #4 ; Shift right by 4 bits: R7 should be 0x0f0f0f0f. + + ; Put the expected value in R9 + loadwl R9, value2 + + ; Check to see if it's correct. + assertr R9,R7 + + ; Test asr. +test5: + loadwl R7, value3 + addui R8, R0, #16 + asr R9, R7,R8 + assertv R9, $fffff0f0 + +test6: + loadwl R7, value2 + addui R8, R0, #16 + asr R9, R7,R8 + assertv R9, $f0f + + ; Test asri. +test7: + loadwl R7, value3 + asri R9, R7,#16 + assertv R9, $fffff0f0 + +test8: + loadwl R7, value2 + asri R9, R7,#16 + assertv R9, $f0f + + ; Test shifts of 32 bits and make sure it results in 0. + +pass: + pass + + + .data + .align 4 +value1: .word 0x1 +value2: .word 0x0f0f0f0f +value3: .word 0xf0f0f0f0 diff --git a/sid/component/testsuite/sidcomp.cgen-cpu.ms1/subinsns.s b/sid/component/testsuite/sidcomp.cgen-cpu.ms1/subinsns.s new file mode 100644 index 0000000000..a0db41637b --- /dev/null +++ b/sid/component/testsuite/sidcomp.cgen-cpu.ms1/subinsns.s @@ -0,0 +1,62 @@ +# mach(): ms1 + + .include "testutils.inc" + start + + loadwl R6, value1 + loadwl R7, value2 + + assertv R6,$1 + +test1: ; test sub + sub R8,R7,R6 + assertv R8, $1233 + +test2: ; test subi + subi R8, R8, #1 + assertv R8, $1232 + + +test3: ; test subi for negative values + addui R8, R0, #0 ; Clear R8: R8 contains 0. + loadval R8, -4 ; Put expected result in R8. + loadwl R6, value1 ; R6 contains 1. + subi R6, R6, #5 ; R6 = R6 - 5 = -4. + assertv R6, -4 + ei + addi R8, R0, #1 ; Put new expected value in R8. + subi R6, R6, #-5 ; R6 = R6 - -5 = 1. + ei + assertv R6, 1 + +test4: ;test subui + loadwl R6 value2 + subui R8, R6, #1 + assertv R8, $1233 + +test5: ; test subu + loadwl R6, value3 ; R6 should contain 0xfffffffe + loadval R7,1 ; R7 should contain 0xfffffffe + subu R8, R6, R7 + assertv R8, 0xfffffffd + +test6: ; test subu + loadval R6, 0xfffffffe ; R6 should contain 0xfffffffe + loadval R7,1 ; R7 should contain 0xfffffffe + subu R8, R6, R7 + assertv R8, 0xfffffffd + +test7: ; test sub with same case as subu + loadval R6, 0xfffffffe ; R6 should contain 0xfffffffe + loadval R7,1 ; R7 should contain 0xfffffffe + subu R8, R6, R7 + assertv R8, -3 + +pass: + pass + + .data + .align 4 +value1: .word 0x0001 +value2: .word 0x1234 +value3: .word 0xfffffffe diff --git a/sid/component/testsuite/sidcomp.cgen-cpu.ms1/test-img.x b/sid/component/testsuite/sidcomp.cgen-cpu.ms1/test-img.x new file mode 100755 index 0000000000000000000000000000000000000000..5aa6f801df6f9be7dc8132455398d5bbc1d7859e GIT binary patch literal 14360 zcmeI3e|()+S-_t+_h!9gg}wJC>jF#Mdy{m8Evq*_F3pyz_ub7{gp4Ka?Uq7?WNS;1 zZp+$WvsuRlibSj$pkTqOVRTSO)sz*ev}!x56e$|Dn^n6RwPMvNQL7XecKtr*ocAW_ z+PdQBD-f^pS&8SL z6G`#qQbM-*)X`cjS>LQ>JN#+$j!k>x@%d@4xP;X0(MHF#t-tP-@}AhUrJ2;Tho$aH z>iR@sZQU#2CksUnjq@L){3j%?b+vu6bXIBdp9oA_9TToiedmcAPusTNG-29yc^*1? z6-X?4xBlq-d|Tg5GxO81Ly$iuwW=5PsIm1H)`m%|x0dbnWm2hP^Y2VV`4RI+#LxQD zZOWiStp3i#`DMK%Hc#7nLdr*VM)q7TrQLIF*mBg_IG0xFt}}JpypCYn>SWRiYw5pd z>OVduq4o)V8HXCiA<*Y&Ea-C$eXe$W_EWZewJYyazUETpZNJL;nK@z8BK-;jb&Nr* z&FPu3dR}fj|8x1c8n_77!UPQ9m9P=M z0ye>`U^83{Gw_wL9li>7z^ma3=))XL!Y-JC-LMMwz-rhFuYm=)1op#gp^jY*9DuKe z>)>nP5WEgHo)z$5st&9a0k2r?u4&}yI>QX zfUkqQ;f-()yb11w&2SRl4EMuj@BsWlcnD_TVb}tX!d7?;w!!1D9Ztb4JON)1Pr~K! z6zqW0@D_L)-U`paPWU`r0cYS3!L#s(;W_vta2DqBM;LrhLKug)!3501#jp$d@OD@Y z-vDdi9k3R5!vOv$Y=m!wP4G>y8TP;oyc4#=H^UBi7hC~*VGj1eF1QkQ!&R^c7GN)2 z4GZvY*bnc4YhgbefNS77_!c+>-wHRvwQv~z7#x9bgQM{6a4Q^uMK}nz!F%Btybo@N z>)<$C4|l)~a3_2R+y#f=1bipl4SyW&f$xHQ;YK(K?}z*01MmQR5FUcV@GyJ`9)+9W zF}N8Xha+$bz8ju^KLJm|E$|c^h12k1cp5$e&%mFA&%>>72L2R03m=8&;CtXKEas0? z2z)P$!}q}id_PXW{R_bMSZJEIgb)5)*g?#^F;i0lxwl!=uoLzXz+~@537SRags; z!2o^@Ho`xEP4Mfm86Jlj_zl<&{}6V-KY}aZ6wJXthF$PaU^o0z*aJ_%UidUDz-M4T z{4=-~o`eJN&*3`w7jOvvCEN&4!D09;9D&clQTSJIE1ZT!_}6e7{2Mq1{}yhCr{OsK zJGcXW6Yhk64|l;ca031V+ztN`?t%XV_rmAlB>ZQ%AN~tG0KWwf!5MfM{wq8R{|z34 z{|=ACvv3Oj2Rs4)6P|?MhNs{;I1Rr8Ps9I$XW$F)c{mGa;CJC!_#!-)N=}N66JoR8 zvvCs-&5Lt_{L@lhM|>Gueb;O`&U=Q~D>-1|Jrnb+v~fy!lV{>LP0LQ2y=*Le(#E7- zgcDpu)mLM* zx~tIhV6%;@_O9&oVG#C z*GT^ZjUS0~Yh(4;<7whNjeDPQIyKmO!d6%B5oyc@vQA^WaH+Gy>QYJTYw4AabRYdr z(Qo=34$=qm@=uAc@vOI@G#m1)WmVcLOVi4*-hS8T&Y-l{#*KH)MsakQk`>WAv~Av> zALkM`H^%C_c50a@J&I>F=A>_atnIGZR5B2?XV{`P%}kl{YE$}qeq0%~=f+ziQ+9{4vJ= z;4L#{o3sVuT}hn>dnKf-riZR1Cc)8j&EAJ?YXYkmVH=O z)Uh_4t<4#Mvq+Pvn|>S8@2GBP`;5L5>nhZSp>0#D=-+MjdH$Ix+vm-=bEF@B*yfu) zsGhI(j+#09HLGWQ4ae)WFL~+}$g(Dv)IT)vPt2$<8~2 z1IA`%9${O3=Own=fbG0e>4Ns!SBl5Kz&tc(A^POzk1RnKo;6)=nB<()D^;JzcVwOK zSSj)BW*M%F7p1PUD6-9$*lM|2+i&TUfcDN&m+>?BB`=?n_;Pu1m$CIG*8clTXZ@BU zeGxC!6!3md@}%p0!H-nZw)Igh5^pKUM%6>@W&C8aP#arasAe6Sajc6m-hDLOkQ1qL zV;#z3V~dsUoz;aJEu(33WnQ#xPzK%XJivyrwz+lVZL)gcv&OW2eV?*hQ}qMfH5B~( zHRgLk$4ojVogJB@t&*tPN59kB?^2Jx%bIOseKi_?c7$_Vy-nTWcCAG+JxL2;!c4JBA&ET+v z@3uD4{Omn4*6=Qgg>SKGUIlCS9^2P&mGj-S>9>wc{t@na)-XPwm4sRMx9PgSWvWW| z5}rHMzfh<5R^GS!iCsIcU+gFLoKL^BoQhjZO&)E|*Q@iM(y(_>D(rmhP2gM17#W>c zapqDz`>cL`YFy$U&*^-z^RBw`nCovMpLFA<fF8`>Qp9gbnsRUB6Xr;;BtzUAIi- zN$<$nJ}_1}?MKT81r(si7}fX3}S zZ%KO@ofCe${hswTUM$UOT6&+vV)cxDYFP4L$IomjO89|!bD-be1$nP1&C<@*WxKw{ z+ST;2v7%qu7O#ja!_{-|clMX2G>!4{lC-7IoqlP;8uAj{ zm)V`3#$v4P@EX@2^r#wSO|m}ZZssjMn;0)q6_Q5#+J7_W>t9k=kD2q)JbuXPs(R*m z#(qPp&-^tMtsm{Pt{+o3^EyV|ksndNVe*;xb9%opt!-%;)m8nE++7sax#~9b_T zDcjcg9IIC%KkDimwf)V%&$gTYpd_?iXxnR_^Nq{pg<)+^=aSz}u(r>RX=gAy?OjJd zFF9{!4{N`)57>K{nAOa2o_#NGpR<89sXs95lJyx&THCc$$ze@v_^@2zRZEA~qkh1y z$BD8p(7LmaNPnt}IpOTC^RTX>C_X+!V^{fzohNN6=SR2L{_DG)kCcupLuYHN>kGS- zxQKS8jaPbQX%&71f30Z?d=zQeX~@1?I>8-qjDDCHtF5Kf?KR3m4<_ne<^{4)7*^0&m2l~H~*c1hXxUOYqIR`-00v&y4$bC`XNvCntNVly{7 z80RhQ3HWWDBQJ0KzhlN<>o;S?o_B$`!f>9V_pkJ)bO>@6@XAjP~GY-RO9g_ojJkNc#}&VY>bn?px=^be_)}w-w$^ z7a6xfyG|IF8v6UvaT~PzsrpUw7mnLtdE8Es7meE#zUWcnn>g`}IcspYZ`O_K?DqQj z%g8UEg^7WDV!W+-22Ry;eq;Smcda=iti^h^r3+b4gHtlJAn>rYnHnVBz&~{xc zVq*`=YTBjFwxNp;wOrOO9aZKBb?ui9Xdas4gasbM>meru-2Jvc0lj*E>FG zQqv;e=e>n}Z+Eo*N-t_({IHk4utz^WEa8)OUF-g>v4p;>lHD9@^wZ-SpLFE-LTV;ivRl7;nVyJa}F1z#JwaX8=CuC#Ng z>}$K`bn5JOzP8)#GkY9&+cNnNIlfUAvvzhxdk22FS^HxA@4eCZ%Up~|8vQhL1)e(3 z|F(Oty~sN5E3adpe!p}b_m$W24EYP!abI~IpCB(<$H%-y@~G;{Txpgyy?VwsF>4s@ zy;0v8tL5_D-8#oitim~oSj3d=Oj|qUZ*=y#(b?s(GO^Eh*D;s9@G(2bw`W2w5}2ATue-7+IDB|Aa?MFXY@Veiy&ioK))~Oo0}`F ze|rX4(4SI4`)d44! z(D`I(Tf8zTr`faL!a9hFO7Zo+=-RHT#t)+N{C;Ggl zBynMVp_cvH*gSu`iK%yJ-o?gz!QJmF`=0g(wQEytfxBnOoz}GI{H?mDHu%_o?*1aR zI=JjHM5mX156ir4%vO1OjjfZ?qg3H<0`_?5!x%N1yp;5$TkKsd=M_`NlPE}SE7JqM;f?${0Wj-7Wy zcgL>JE@o>?B{Mol?Y$N07rLurPM*+MD7ur^_vz<|sq>|G^4;l++{tTsy$3%3Za%v2 z)qL*gjbFwlqYM6v4!imwbjeGm$GY~JAb!-X#MyIV>j$!{x(JDH}>## zA4nww(S3?J=*14+-lgTE*wnRMZFHo((&SHb4x=vWOAt@S?YtaBb;CJE%tq4?D%DRby(P%U+>zWjJ`|UY}(>}+|)(e2{%XlRDDtBNIaFyX&csoZ37r z>7@9{EyVi|4NGbZZP`0VQ@^$moi{jd`wf(B)b~ioCMVL@YMYV1>;bB88+DMsP~V)@ zH;2CQKpI-mtChN{ebc_`WAvi_fcxu!KBTk{q#NB-PxP+iT;ijr>FcK9OX^!spctU5 z_Ak=6!RVWF_AOd{$DF?CR<~xnA3=V~O8t$m3q;3A?O<$zevHBXl-dEmqVa{!8y$meC->XTm1Ijf zj$4e4`3=48YiFi(hI+hOVRF8+40gTH%~gu86*tMdepR*lpVA9e)QclAq~9SK%JV` zS=9T@qNx{O8Ke&Sb8|Ln`xnhwEsu>(r=IXt|5|=0!0&;vRi#y zpIUOVHeQLpS3jh_t}Eb7+1;#lsSi>=rO(-3yLRJO(WYH9*6&lF=Cj7n_f55_YkXl1 zT~Ey8#p5|s5Blwlr->~qZU6YbH6AnjgweOGD|H%Oud(w~+h_^wo~F86kqW|{$4%H7E8egsLsjpUB%x~A&(Awfs{`vem@bPo@eVKLCGSBVrvaz>2 zpY(c3?wpTUyAw+o`$y*sbEiRHxX+08f197QywVq50>JGy9F%^L4&y zeqE_Nvc)Bh~)R`=5JWDuwy>{m=I;aCsKE)1NEf%cGG5R3Xnu4O9u7@b~q- zDj6poP$lQ28>k$$K$;A9A@3_BTxDn%z_P-Wc7PN*{BWDiuCbaDWy9CmUHs!TaK z300<@oPjDcPR>E3Pn;y6itnTbssv7&pi0I`2UN*9>4qx3PWqwBfRiDpGVEj&suZ1! zL6vbQJE6*ilRZ#n(#Zj+a@ff+s50f`BvhGpat5l*I5`KAmEt4;ReUEkP$h8E1XVIl zI-p95NP^IW(462Mf*$Gu9oa})rlTHpmmBUVsL6s>dC!xx; zlQU3d#>qK|tP&>)sNy@RfhvKMCa98e(g9U+PP(B=uakbLGT>wgsth|Bg(^iSV^C$> z$xf&;;bad~nRIdhsvLH545~~yISEy!ot%LxGfvLIbHd$_eoB1o)8+q+-i^p#k>_s> zn(lb>>emHr%UW)}|G`beLl54ZX~}f7W{8@}WuN)1xo#1;y3%E~IPL+!4D^QM8?gh)KqtkLoVJ+oO^F05fdHPv{Xgl