From 9ecbcab4f49189c308e0f271d21114ddb5a35b16 Mon Sep 17 00:00:00 2001
From: Sanjay Patel <spatel@rotateright.com>
Date: Mon, 24 Apr 2017 22:42:34 +0000
Subject: [PATCH] [ARM, x86] add more vector tests for bool math; NFC

I'm proposing a fold for increment-of-sexted-bool in:
https://reviews.llvm.org/D31944
...so we need to know what happens in more cases like these.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301269 91177308-0d34-0410-b5e6-96231b3b80d8
---
 test/CodeGen/ARM/bool-ext-inc.ll | 39 +++++++++++++++++++++++++++++++++++++++
 test/CodeGen/X86/bool-ext-inc.ll | 25 +++++++++++++++++++++++++
 2 files changed, 64 insertions(+)

diff --git a/test/CodeGen/ARM/bool-ext-inc.ll b/test/CodeGen/ARM/bool-ext-inc.ll
index fe43f1b2ef9..b91b9b25899 100644
--- a/test/CodeGen/ARM/bool-ext-inc.ll
+++ b/test/CodeGen/ARM/bool-ext-inc.ll
@@ -30,3 +30,42 @@ define <4 x i32> @sext_inc_vec(<4 x i1> %x) {
   ret <4 x i32> %add
 }
 
+define <4 x i32> @cmpgt_sext_inc_vec(<4 x i32> %x, <4 x i32> %y) {
+; CHECK-LABEL: cmpgt_sext_inc_vec:
+; CHECK:       @ BB#0:
+; CHECK-NEXT:    mov r12, sp
+; CHECK-NEXT:    vmov d19, r2, r3
+; CHECK-NEXT:    vmov.i32 q10, #0x1
+; CHECK-NEXT:    vld1.64 {d16, d17}, [r12]
+; CHECK-NEXT:    vmov d18, r0, r1
+; CHECK-NEXT:    vcgt.s32 q8, q9, q8
+; CHECK-NEXT:    vadd.i32 q8, q8, q10
+; CHECK-NEXT:    vmov r0, r1, d16
+; CHECK-NEXT:    vmov r2, r3, d17
+; CHECK-NEXT:    mov pc, lr
+  %cmp = icmp sgt <4 x i32> %x, %y
+  %ext = sext <4 x i1> %cmp to <4 x i32>
+  %add = add <4 x i32> %ext, <i32 1, i32 1, i32 1, i32 1>
+  ret <4 x i32> %add
+}
+
+define <4 x i32> @cmpne_sext_inc_vec(<4 x i32> %x, <4 x i32> %y) {
+; CHECK-LABEL: cmpne_sext_inc_vec:
+; CHECK:       @ BB#0:
+; CHECK-NEXT:    mov r12, sp
+; CHECK-NEXT:    vmov d19, r2, r3
+; CHECK-NEXT:    vld1.64 {d16, d17}, [r12]
+; CHECK-NEXT:    vmov d18, r0, r1
+; CHECK-NEXT:    vceq.i32 q8, q9, q8
+; CHECK-NEXT:    vmov.i32 q9, #0x1
+; CHECK-NEXT:    vmvn q8, q8
+; CHECK-NEXT:    vadd.i32 q8, q8, q9
+; CHECK-NEXT:    vmov r0, r1, d16
+; CHECK-NEXT:    vmov r2, r3, d17
+; CHECK-NEXT:    mov pc, lr
+  %cmp = icmp ne <4 x i32> %x, %y
+  %ext = sext <4 x i1> %cmp to <4 x i32>
+  %add = add <4 x i32> %ext, <i32 1, i32 1, i32 1, i32 1>
+  ret <4 x i32> %add
+}
+
diff --git a/test/CodeGen/X86/bool-ext-inc.ll b/test/CodeGen/X86/bool-ext-inc.ll
index d0967c10214..6f3a55f2610 100644
--- a/test/CodeGen/X86/bool-ext-inc.ll
+++ b/test/CodeGen/X86/bool-ext-inc.ll
@@ -29,4 +29,29 @@ define <4 x i32> @sext_inc_vec(<4 x i1> %x) nounwind {
   ret <4 x i32> %add
 }
 
+define <4 x i32> @cmpgt_sext_inc_vec(<4 x i32> %x, <4 x i32> %y) nounwind {
+; CHECK-LABEL: cmpgt_sext_inc_vec:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    pcmpgtd %xmm1, %xmm0
+; CHECK-NEXT:    paddd {{.*}}(%rip), %xmm0
+; CHECK-NEXT:    retq
+  %cmp = icmp sgt <4 x i32> %x, %y
+  %ext = sext <4 x i1> %cmp to <4 x i32>
+  %add = add <4 x i32> %ext, <i32 1, i32 1, i32 1, i32 1>
+  ret <4 x i32> %add
+}
+
+define <4 x i32> @cmpne_sext_inc_vec(<4 x i32> %x, <4 x i32> %y) nounwind {
+; CHECK-LABEL: cmpne_sext_inc_vec:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    pcmpeqd %xmm1, %xmm0
+; CHECK-NEXT:    pcmpeqd %xmm1, %xmm1
+; CHECK-NEXT:    pxor %xmm1, %xmm0
+; CHECK-NEXT:    paddd {{.*}}(%rip), %xmm0
+; CHECK-NEXT:    retq
+  %cmp = icmp ne <4 x i32> %x, %y
+  %ext = sext <4 x i1> %cmp to <4 x i32>
+  %add = add <4 x i32> %ext, <i32 1, i32 1, i32 1, i32 1>
+  ret <4 x i32> %add
+}
 
-- 
2.11.0