From 9f570b6c240e4f64791805b37fb4c60c65ea95c6 Mon Sep 17 00:00:00 2001 From: Manikanta Maddireddy Date: Tue, 18 Jun 2019 23:31:54 +0530 Subject: [PATCH] PCI: tegra: Update flow control timer frequency in Tegra210 Recommended UpdateFC threshold in Tegra210 is 0x60 for best performance of x1 link. Setting this to 0x60 provides the best balance between number of UpdateFC packets and read data sent over the link. UpdateFC timer frequency is equal to twice the value of register content in nsec, i.e (2 * 0x60) = 192 nsec. Signed-off-by: Manikanta Maddireddy Signed-off-by: Lorenzo Pieralisi Acked-by: Thierry Reding --- drivers/pci/controller/pci-tegra.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c index 95e27c08e8bd..cf2398a10d8c 100644 --- a/drivers/pci/controller/pci-tegra.c +++ b/drivers/pci/controller/pci-tegra.c @@ -320,6 +320,7 @@ struct tegra_pcie_soc { bool update_clamp_threshold; bool program_deskew_time; bool raw_violation_fixup; + bool update_fc_timer; struct { struct { u32 rp_ectl_2_r1; @@ -668,6 +669,13 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port) value |= soc->update_fc_threshold; writel(value, port->base + RP_VEND_XP); } + + if (soc->update_fc_timer) { + value = readl(port->base + RP_VEND_XP); + value &= ~RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK; + value |= soc->update_fc_threshold; + writel(value, port->base + RP_VEND_XP); + } } static void tegra_pcie_port_enable(struct tegra_pcie_port *port) @@ -2429,6 +2437,7 @@ static const struct tegra_pcie_soc tegra20_pcie = { .update_clamp_threshold = false, .program_deskew_time = false, .raw_violation_fixup = false, + .update_fc_timer = false, .ectl.enable = false, }; @@ -2456,6 +2465,7 @@ static const struct tegra_pcie_soc tegra30_pcie = { .update_clamp_threshold = false, .program_deskew_time = false, .raw_violation_fixup = false, + .update_fc_timer = false, .ectl.enable = false, }; @@ -2478,6 +2488,7 @@ static const struct tegra_pcie_soc tegra124_pcie = { .update_clamp_threshold = true, .program_deskew_time = false, .raw_violation_fixup = true, + .update_fc_timer = false, .ectl.enable = false, }; @@ -2488,6 +2499,8 @@ static const struct tegra_pcie_soc tegra210_pcie = { .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, .pads_refclk_cfg0 = 0x90b890b8, + /* FC threshold is bit[25:18] */ + .update_fc_threshold = 0x01800000, .has_pex_clkreq_en = true, .has_pex_bias_ctrl = true, .has_intr_prsnt_sense = true, @@ -2498,6 +2511,7 @@ static const struct tegra_pcie_soc tegra210_pcie = { .update_clamp_threshold = true, .program_deskew_time = true, .raw_violation_fixup = false, + .update_fc_timer = true, .ectl = { .regs = { .rp_ectl_2_r1 = 0x0000000f, @@ -2537,6 +2551,7 @@ static const struct tegra_pcie_soc tegra186_pcie = { .update_clamp_threshold = false, .program_deskew_time = false, .raw_violation_fixup = false, + .update_fc_timer = false, .ectl.enable = false, }; -- 2.11.0