From a064d28843b425905ed981e693b7730a183ee31b Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Sun, 19 Mar 2006 01:13:28 +0000 Subject: [PATCH] rename these nodes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26848 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCISelLowering.cpp | 6 +++--- lib/Target/X86/X86ISelLowering.cpp | 18 +++++++++--------- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index c3583771e8e..9963203dfca 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -179,10 +179,10 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM) setOperationAction(ISD::LOAD , MVT::v4f32, Legal); setOperationAction(ISD::ADD , MVT::v4i32, Legal); setOperationAction(ISD::LOAD , MVT::v4i32, Legal); - // FIXME: We don't support any ConstantVec's yet. We should custom expand + // FIXME: We don't support any BUILD_VECTOR's yet. We should custom expand // the ones we do! - setOperationAction(ISD::ConstantVec, MVT::v4f32, Expand); - setOperationAction(ISD::ConstantVec, MVT::v4i32, Expand); + setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Expand); + setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Expand); } setSetCCResultContents(ZeroOrOneSetCCResult); diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index a9f09b5ee6d..4414c6880eb 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -263,9 +263,9 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM) addRegisterClass(MVT::v2i32, X86::VR64RegisterClass); // FIXME: add MMX packed arithmetics - setOperationAction(ISD::ConstantVec, MVT::v8i8, Expand); - setOperationAction(ISD::ConstantVec, MVT::v4i16, Expand); - setOperationAction(ISD::ConstantVec, MVT::v2i32, Expand); + setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Expand); + setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand); + setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Expand); } if (TM.getSubtarget().hasSSE1()) { @@ -275,7 +275,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM) setOperationAction(ISD::SUB , MVT::v4f32, Legal); setOperationAction(ISD::MUL , MVT::v4f32, Legal); setOperationAction(ISD::LOAD , MVT::v4f32, Legal); - setOperationAction(ISD::ConstantVec, MVT::v4f32, Expand); + setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Expand); } if (TM.getSubtarget().hasSSE2()) { @@ -290,11 +290,11 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM) setOperationAction(ISD::SUB , MVT::v2f64, Legal); setOperationAction(ISD::MUL , MVT::v2f64, Legal); setOperationAction(ISD::LOAD , MVT::v2f64, Legal); - setOperationAction(ISD::ConstantVec, MVT::v2f64, Expand); - setOperationAction(ISD::ConstantVec, MVT::v16i8, Expand); - setOperationAction(ISD::ConstantVec, MVT::v8i16, Expand); - setOperationAction(ISD::ConstantVec, MVT::v4i32, Expand); - setOperationAction(ISD::ConstantVec, MVT::v2i64, Expand); + setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Expand); + setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Expand); + setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Expand); + setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Expand); + setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Expand); } computeRegisterProperties(); -- 2.11.0