From a0ae75470a29ae78d3224a21f4ecbf5926f6faa2 Mon Sep 17 00:00:00 2001 From: Matthias Braun Date: Wed, 22 Feb 2017 19:16:33 +0000 Subject: [PATCH] Bring back 2>&1 redirection for this test git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295864 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/Hexagon/expand-condsets-rm-reg.mir | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir b/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir index 4a4a5e143ee..f3d105f75da 100644 --- a/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir +++ b/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass expand-condsets -o - %s -verify-machineinstrs -debug-only=expand-condsets | FileCheck %s +# RUN: llc -march=hexagon -run-pass expand-condsets -o - %s -verify-machineinstrs -debug-only=expand-condsets 2>&1 | FileCheck %s # REQUIRES: asserts # Check that coalesced registers are removed from live intervals. -- 2.11.0