From a1ddc3269226eaae200c81855e7484e59875c062 Mon Sep 17 00:00:00 2001 From: astoria-d Date: Sat, 12 Oct 2013 09:49:08 +0900 Subject: [PATCH] test vga output working... --- tools/qt_proj_test5/qt_proj_test5.vhd | 40 +++++++++++++++++------------------ tools/qt_proj_test5/vga.vhd | 40 ++++++----------------------------- 2 files changed, 26 insertions(+), 54 deletions(-) diff --git a/tools/qt_proj_test5/qt_proj_test5.vhd b/tools/qt_proj_test5/qt_proj_test5.vhd index 9264fc1..699853f 100644 --- a/tools/qt_proj_test5/qt_proj_test5.vhd +++ b/tools/qt_proj_test5/qt_proj_test5.vhd @@ -29,7 +29,7 @@ entity qt_proj_test5 is base_clk : in std_logic; - base_clk_27mhz : in std_logic; +-- base_clk_27mhz : in std_logic; rst_n : in std_logic; h_sync_n : out std_logic; v_sync_n : out std_logic; @@ -194,27 +194,31 @@ end component; begin + --ppu/cpu clock generator + clock_inst : clock_divider port map + (base_clk, rst_n, cpu_clk, ppu_clk, vga_clk); --- ppu_inst: dummy_ppu --- port map ( ppu_clk , --- rst_n , --- pos_x , --- pos_y , --- nes_r , --- nes_g , --- nes_b --- ); - - vga_clk_gen_inst : vga_clk_gen - PORT map - ( - base_clk_27mhz, vga_clk_pll + ppu_inst: dummy_ppu + port map ( ppu_clk , + rst_n , + pos_x , + pos_y , + nes_r , + nes_g , + nes_b ); +-- vga_clk_gen_inst : vga_clk_gen +-- PORT map +-- ( +-- base_clk_27mhz, vga_clk_pll +-- ); + vga_ctl_inst : vga_ctl port map ( ppu_clk , - vga_clk_pll, + --vga_clk_pll, + ppu_clk , --vga_clk , rst_n , pos_x , @@ -241,10 +245,6 @@ begin -- dbg_addr <= addr; -- dbg_d_io <= d_io; -- --- --ppu/cpu clock generator --- clock_inst : clock_divider port map --- (base_clk, rst_n, cpu_clk, ppu_clk, vga_clk); --- -- dbg_cpu_clk <= cpu_clk; -- dbg_ppu_clk <= ppu_clk; -- diff --git a/tools/qt_proj_test5/vga.vhd b/tools/qt_proj_test5/vga.vhd index 7c2d248..21a4127 100644 --- a/tools/qt_proj_test5/vga.vhd +++ b/tools/qt_proj_test5/vga.vhd @@ -144,34 +144,6 @@ signal cnt_clk : std_logic; begin --- ppu_clk_p : process (rst_n, ppu_clk) --- begin --- if (rst_n = '0') then --- h_sync_n <= '1'; --- v_sync_n <= '1'; --- elsif (rising_edge(ppu_clk)) then --- --- --sync signal assert. --- if (pos_x >= conv_std_logic_vector((VGA_W + H_FP) * 341/800, 9) and --- pos_x < conv_std_logic_vector((VGA_W + H_FP + H_SP) * 341/800, 9)) then --- h_sync_n <= '0'; --- --- --d_print("vga_ctl: h_sync."); --- else --- h_sync_n <= '1'; --- end if; --- --- if (pos_y >= conv_std_logic_vector((VGA_H + V_FP) * 262/525, 9) and --- pos_y < conv_std_logic_vector((VGA_H + V_FP + V_SP) * 262/525, 9)) then --- v_sync_n <= '0'; --- --- --d_print("vga_ctl: v_sync."); --- else --- v_sync_n <= '1'; --- end if; --- end if; --- end process; - cnt_clk <= not vga_clk; x_inst : counter_register generic map (10, 1) port map (cnt_clk , x_res_n, '0', '1', (others => '0'), vga_x); @@ -207,23 +179,23 @@ begin end if; --sync signal assert. - if (vga_x >= conv_std_logic_vector(VGA_W + H_FP, 10) and - vga_x < conv_std_logic_vector(VGA_W + H_FP + H_SP , 10)) then + if (vga_x >= conv_std_logic_vector((VGA_W + H_FP) * 341/800, 10) and + vga_x < conv_std_logic_vector((VGA_W + H_FP + H_SP) * 341/800, 10)) then h_sync_n <= '0'; else h_sync_n <= '1'; end if; - if (vga_y >= conv_std_logic_vector(VGA_H + V_FP, 10) and - vga_y < conv_std_logic_vector(VGA_H + V_FP + V_SP, 10)) then + if (vga_y >= conv_std_logic_vector((VGA_H + V_FP) * 262/525, 10) and + vga_y < conv_std_logic_vector((VGA_H + V_FP + V_SP) * 262/525, 10)) then v_sync_n <= '0'; else v_sync_n <= '1'; end if; - if (vga_y <=conv_std_logic_vector(VGA_H, 10)) then - if (vga_x < conv_std_logic_vector(VGA_W, 10)) then + if (vga_y <=conv_std_logic_vector((VGA_H) * 341/800, 10)) then + if (vga_x < conv_std_logic_vector((VGA_W) * 262/525, 10)) then -- r<=nes_r; -- g<=nes_g; -- b<=nes_b; -- 2.11.0