From a4073f45f603391a3417f57fda76b04c7d1b21bb Mon Sep 17 00:00:00 2001 From: Michael Berg Date: Wed, 6 Feb 2019 19:57:06 +0000 Subject: [PATCH] Move IR flag handling directly into builder calls for cases translated from Instructions in GlobalIsel Reviewers: aditya_nandakumar, volkan Reviewed By: aditya_nandakumar Subscribers: rovka, kristof.beyls, volkan, Petar.Avramovic Differential Revision: https://reviews.llvm.org/D57630 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353336 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/MachineInstr.h | 2 ++ lib/CodeGen/GlobalISel/IRTranslator.cpp | 62 ++++++++++++++++----------------- lib/CodeGen/MachineInstr.cpp | 29 +++++++++------ 3 files changed, 50 insertions(+), 43 deletions(-) diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h index faeb66ea227..5267b9db21a 100644 --- a/include/llvm/CodeGen/MachineInstr.h +++ b/include/llvm/CodeGen/MachineInstr.h @@ -1538,6 +1538,8 @@ public: /// not modify the MIFlags of this MachineInstr. uint16_t mergeFlagsWith(const MachineInstr& Other) const; + static uint16_t copyFlagsFromInstruction(const Instruction &I); + /// Copy all flags to MachineInst MIFlags void copyIRFlags(const Instruction &I); diff --git a/lib/CodeGen/GlobalISel/IRTranslator.cpp b/lib/CodeGen/GlobalISel/IRTranslator.cpp index ea02ea74734..c6cb17c2b0d 100644 --- a/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -320,12 +320,13 @@ bool IRTranslator::translateBinaryOp(unsigned Opcode, const User &U, unsigned Op0 = getOrCreateVReg(*U.getOperand(0)); unsigned Op1 = getOrCreateVReg(*U.getOperand(1)); unsigned Res = getOrCreateVReg(U); - auto FBinOp = MIRBuilder.buildInstr(Opcode).addDef(Res).addUse(Op0).addUse(Op1); + uint16_t Flags = 0; if (isa(U)) { - MachineInstr *FBinOpMI = FBinOp.getInstr(); const Instruction &I = cast(U); - FBinOpMI->copyIRFlags(I); + Flags = MachineInstr::copyFlagsFromInstruction(I); } + + MIRBuilder.buildInstr(Opcode, {Res}, {Op0, Op1}, Flags); return true; } @@ -366,8 +367,8 @@ bool IRTranslator::translateCompare(const User &U, MIRBuilder.buildCopy( Res, getOrCreateVReg(*Constant::getAllOnesValue(CI->getType()))); else { - auto FCmp = MIRBuilder.buildFCmp(Pred, Res, Op0, Op1); - FCmp->copyIRFlags(*CI); + MIRBuilder.buildInstr(TargetOpcode::G_FCMP, {Res}, {Pred, Op0, Op1}, + MachineInstr::copyFlagsFromInstruction(*CI)); } return true; @@ -602,13 +603,13 @@ bool IRTranslator::translateSelect(const User &U, ArrayRef Op1Regs = getOrCreateVRegs(*U.getOperand(2)); const SelectInst &SI = cast(U); - const CmpInst *Cmp = dyn_cast(SI.getCondition()); + uint16_t Flags = 0; + if (const CmpInst *Cmp = dyn_cast(SI.getCondition())) + Flags = MachineInstr::copyFlagsFromInstruction(*Cmp); + for (unsigned i = 0; i < ResRegs.size(); ++i) { - auto Select = - MIRBuilder.buildSelect(ResRegs[i], Tst, Op0Regs[i], Op1Regs[i]); - if (Cmp && isa(Cmp)) { - Select->copyIRFlags(*Cmp); - } + MIRBuilder.buildInstr(TargetOpcode::G_SELECT, {ResRegs[i]}, + {Tst, Op0Regs[i], Op1Regs[i]}, Flags); } return true; @@ -833,10 +834,9 @@ bool IRTranslator::translateSimpleUnaryIntrinsic( return false; // Yes. Let's translate it. - auto Inst = MIRBuilder.buildInstr(Op) - .addDef(getOrCreateVReg(CI)) - .addUse(getOrCreateVReg(*CI.getArgOperand(0))); - Inst->copyIRFlags(CI); + MIRBuilder.buildInstr(Op, {getOrCreateVReg(CI)}, + {getOrCreateVReg(*CI.getArgOperand(0))}, + MachineInstr::copyFlagsFromInstruction(CI)); return true; } @@ -969,20 +969,18 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID, case Intrinsic::smul_with_overflow: return translateOverflowIntrinsic(CI, TargetOpcode::G_SMULO, MIRBuilder); case Intrinsic::pow: { - auto Pow = MIRBuilder.buildInstr(TargetOpcode::G_FPOW) - .addDef(getOrCreateVReg(CI)) - .addUse(getOrCreateVReg(*CI.getArgOperand(0))) - .addUse(getOrCreateVReg(*CI.getArgOperand(1))); - Pow->copyIRFlags(CI); + MIRBuilder.buildInstr(TargetOpcode::G_FPOW, {getOrCreateVReg(CI)}, + {getOrCreateVReg(*CI.getArgOperand(0)), + getOrCreateVReg(*CI.getArgOperand(1))}, + MachineInstr::copyFlagsFromInstruction(CI)); return true; } case Intrinsic::fma: { - auto FMA = MIRBuilder.buildInstr(TargetOpcode::G_FMA) - .addDef(getOrCreateVReg(CI)) - .addUse(getOrCreateVReg(*CI.getArgOperand(0))) - .addUse(getOrCreateVReg(*CI.getArgOperand(1))) - .addUse(getOrCreateVReg(*CI.getArgOperand(2))); - FMA->copyIRFlags(CI); + MIRBuilder.buildInstr(TargetOpcode::G_FMA, {getOrCreateVReg(CI)}, + {getOrCreateVReg(*CI.getArgOperand(0)), + getOrCreateVReg(*CI.getArgOperand(1)), + getOrCreateVReg(*CI.getArgOperand(2))}, + MachineInstr::copyFlagsFromInstruction(CI)); return true; } case Intrinsic::fmuladd: { @@ -996,14 +994,14 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID, TLI.isFMAFasterThanFMulAndFAdd(TLI.getValueType(*DL, CI.getType()))) { // TODO: Revisit this to see if we should move this part of the // lowering to the combiner. - auto FMA = MIRBuilder.buildInstr(TargetOpcode::G_FMA, {Dst}, {Op0, Op1, Op2}); - FMA->copyIRFlags(CI); + MIRBuilder.buildInstr(TargetOpcode::G_FMA, {Dst}, {Op0, Op1, Op2}, + MachineInstr::copyFlagsFromInstruction(CI)); } else { LLT Ty = getLLTForType(*CI.getType(), *DL); - auto FMul = MIRBuilder.buildInstr(TargetOpcode::G_FMUL, {Ty}, {Op0, Op1}); - FMul->copyIRFlags(CI); - auto FAdd = MIRBuilder.buildInstr(TargetOpcode::G_FADD, {Dst}, {FMul, Op2}); - FAdd->copyIRFlags(CI); + auto FMul = MIRBuilder.buildInstr(TargetOpcode::G_FMUL, {Ty}, {Op0, Op1}, + MachineInstr::copyFlagsFromInstruction(CI)); + MIRBuilder.buildInstr(TargetOpcode::G_FADD, {Dst}, {FMul, Op2}, + MachineInstr::copyFlagsFromInstruction(CI)); } return true; } diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp index 7ef931a6636..4c80b7bfb0b 100644 --- a/lib/CodeGen/MachineInstr.cpp +++ b/lib/CodeGen/MachineInstr.cpp @@ -519,39 +519,46 @@ uint16_t MachineInstr::mergeFlagsWith(const MachineInstr &Other) const { return getFlags() | Other.getFlags(); } -void MachineInstr::copyIRFlags(const Instruction &I) { +uint16_t MachineInstr::copyFlagsFromInstruction(const Instruction &I) { + uint16_t MIFlags = 0; // Copy the wrapping flags. if (const OverflowingBinaryOperator *OB = dyn_cast(&I)) { if (OB->hasNoSignedWrap()) - setFlag(MachineInstr::MIFlag::NoSWrap); + MIFlags |= MachineInstr::MIFlag::NoSWrap; if (OB->hasNoUnsignedWrap()) - setFlag(MachineInstr::MIFlag::NoUWrap); + MIFlags |= MachineInstr::MIFlag::NoUWrap; } // Copy the exact flag. if (const PossiblyExactOperator *PE = dyn_cast(&I)) if (PE->isExact()) - setFlag(MachineInstr::MIFlag::IsExact); + MIFlags |= MachineInstr::MIFlag::IsExact; // Copy the fast-math flags. if (const FPMathOperator *FP = dyn_cast(&I)) { const FastMathFlags Flags = FP->getFastMathFlags(); if (Flags.noNaNs()) - setFlag(MachineInstr::MIFlag::FmNoNans); + MIFlags |= MachineInstr::MIFlag::FmNoNans; if (Flags.noInfs()) - setFlag(MachineInstr::MIFlag::FmNoInfs); + MIFlags |= MachineInstr::MIFlag::FmNoInfs; if (Flags.noSignedZeros()) - setFlag(MachineInstr::MIFlag::FmNsz); + MIFlags |= MachineInstr::MIFlag::FmNsz; if (Flags.allowReciprocal()) - setFlag(MachineInstr::MIFlag::FmArcp); + MIFlags |= MachineInstr::MIFlag::FmArcp; if (Flags.allowContract()) - setFlag(MachineInstr::MIFlag::FmContract); + MIFlags |= MachineInstr::MIFlag::FmContract; if (Flags.approxFunc()) - setFlag(MachineInstr::MIFlag::FmAfn); + MIFlags |= MachineInstr::MIFlag::FmAfn; if (Flags.allowReassoc()) - setFlag(MachineInstr::MIFlag::FmReassoc); + MIFlags |= MachineInstr::MIFlag::FmReassoc; } + + return MIFlags; +} + +void MachineInstr::copyIRFlags(const Instruction &I) { + Flags = copyFlagsFromInstruction(I); } bool MachineInstr::hasPropertyInBundle(uint64_t Mask, QueryType Type) const { -- 2.11.0