From a44da25aa69a7a3588a33607a8067c87b3b5a68e Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Thu, 2 Sep 2021 10:40:10 +1000 Subject: [PATCH] target/riscv: Update the ePMP CSR address Update the ePMP CSRs to match the 0.9.3 ePMP spec https://github.com/riscv/riscv-tee/blob/61455747230a26002d741f64879dd78cc9689323/Smepmp/Smepmp.pdf Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Message-id: 28c908de60b9b04fa20e63d113885c98586053f3.1630543194.git.alistair.francis@wdc.com --- target/riscv/cpu.c | 1 + target/riscv/cpu_bits.h | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 13575c1408..d4d5961807 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -599,6 +599,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), + /* ePMP 0.9.3 */ DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 7330ff5a19..ce9dcc030c 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -210,8 +210,8 @@ #define CSR_MTVAL2 0x34b /* Enhanced Physical Memory Protection (ePMP) */ -#define CSR_MSECCFG 0x390 -#define CSR_MSECCFGH 0x391 +#define CSR_MSECCFG 0x747 +#define CSR_MSECCFGH 0x757 /* Physical Memory Protection */ #define CSR_PMPCFG0 0x3a0 #define CSR_PMPCFG1 0x3a1 -- 2.11.0