From a532c78b1051626789d338cc00a0424f187142fe Mon Sep 17 00:00:00 2001
From: yujiro_kaeko <zyangalianhamster01@gmail.com>
Date: Wed, 13 Jul 2011 10:03:32 +0900
Subject: [PATCH] Change-Id: I137d6edab408f7479f683f5dbf06fc84d2331595

---
 VGADisplay/Verilog/vga_generate.v        | 651 +------------------------------
 VGADisplay/Verilog/vga_top.v             |  33 +-
 VGADisplay/src/vga_generate.nsh          |   8 +
 VGADisplay/src/vga_generate.nsl          |  69 +++-
 VGADisplay/src/{FIFO.nsh => vga_ram.nsh} |   2 +-
 VGADisplay/src/{FIFO.v => vga_ram.v}     |  26 +-
 VGADisplay/src/vga_top.nsl               |  15 +-
 7 files changed, 119 insertions(+), 685 deletions(-)
 rename VGADisplay/src/{FIFO.nsh => vga_ram.nsh} (90%)
 rename VGADisplay/src/{FIFO.v => vga_ram.v} (54%)

diff --git a/VGADisplay/Verilog/vga_generate.v b/VGADisplay/Verilog/vga_generate.v
index 57555a9..6b4d2ca 100644
--- a/VGADisplay/Verilog/vga_generate.v
+++ b/VGADisplay/Verilog/vga_generate.v
@@ -1,653 +1,4 @@
 /*
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Fri Jul 08 20:38:17 2011
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Tue Jul 12 23:16:45 2011
  Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER:
 */
-
-module vga_generate ( p_reset , m_clock , i_pix32_data , o_v_sync , o_h_sync , o_vga_red , o_vga_green , o_vga_blue , o_h_cnt , fi_ack_req_32dot , fo_req_32dot );
-  input p_reset;
-  input m_clock;
-  input [31:0] i_pix32_data;
-  output o_v_sync;
-  output o_h_sync;
-  output [3:0] o_vga_red;
-  output [3:0] o_vga_green;
-  output [3:0] o_vga_blue;
-  output [9:0] o_h_cnt;
-  input fi_ack_req_32dot;
-  output fo_req_32dot;
-  wire fs_disp_data;
-  reg r_v_sync;
-  reg r_h_sync;
-  reg r_h_flg;
-  reg r_vdata_flg;
-  reg r_hdata_flg;
-  reg [9:0] r_h_cnt;
-  reg [18:0] r_v_cnt;
-  reg [4:0] r_bit32_cnt;
-  reg r_flg;
-  reg r_cnt;
-  reg [31:0] r1;
-  reg [31:0] r2;
-  reg r_data_select_flag;
-  wire [3:0] w_red;
-  wire [3:0] w_green;
-  wire [3:0] w_blue;
-  wire w_disp_data;
-  wire _net_0;
-  wire _net_1;
-  wire _net_2;
-  wire _net_3;
-  wire _net_4;
-  wire _net_5;
-  wire _net_6;
-  wire _net_7;
-  wire _net_8;
-  wire _net_9;
-  wire _net_10;
-  wire _net_11;
-  wire _net_12;
-  wire _net_13;
-  wire _net_14;
-  wire _net_15;
-  wire _net_16;
-  wire _net_17;
-  wire _net_18;
-  wire _net_19;
-  wire _net_20;
-  wire _net_21;
-  wire _net_22;
-  wire _net_23;
-  wire _net_24;
-  wire _net_25;
-  wire _net_26;
-  wire _net_27;
-  wire _net_28;
-  wire _net_29;
-  wire _net_30;
-  wire _net_31;
-  wire _net_32;
-  wire _net_33;
-  wire _net_34;
-  wire _net_35;
-  wire _net_36;
-  wire _net_37;
-  wire _net_38;
-  wire _net_39;
-  wire _net_40;
-  wire _net_41;
-  wire _net_42;
-  wire _net_43;
-  wire _net_44;
-  wire _net_45;
-  wire _net_46;
-  wire _net_47;
-  wire _net_48;
-  wire _net_49;
-  wire _net_50;
-  wire _net_51;
-  wire _net_52;
-  wire _net_53;
-  wire _net_54;
-  wire _net_55;
-  wire _net_56;
-  wire _net_57;
-  wire _net_58;
-  wire _net_59;
-  wire _net_60;
-  wire _net_61;
-  wire _net_62;
-  wire _net_63;
-  wire _net_64;
-  wire _net_65;
-  wire _net_66;
-  wire _net_67;
-  wire _net_68;
-  wire _net_69;
-  wire _net_70;
-  wire _net_71;
-  wire _net_72;
-  wire _net_73;
-  wire _net_74;
-  wire _net_75;
-  wire _net_76;
-  wire _net_77;
-  wire _net_78;
-  wire _net_79;
-  wire _net_80;
-  wire _net_81;
-  wire _net_82;
-  wire _net_83;
-  wire _net_84;
-  wire _net_85;
-  wire _net_86;
-  wire _net_87;
-  wire _net_88;
-  wire _net_89;
-  wire _net_90;
-  wire _net_91;
-  wire _net_92;
-  wire _net_93;
-  wire _net_94;
-  wire _net_95;
-  wire _net_96;
-  wire _net_97;
-  wire _net_98;
-  wire _net_99;
-  wire _net_100;
-  wire _net_101;
-  wire _net_102;
-  wire _net_103;
-  wire _net_104;
-  wire _net_105;
-  wire _net_106;
-  wire _net_107;
-  wire _net_108;
-  wire _net_109;
-  wire _net_110;
-  wire _net_111;
-  wire _net_112;
-  wire _net_113;
-  wire _net_114;
-  wire _net_115;
-  wire _net_116;
-  wire _net_117;
-  wire _net_118;
-  wire _net_119;
-  wire _net_120;
-  wire _net_121;
-  wire _net_122;
-  wire _net_123;
-  wire _net_124;
-  wire _net_125;
-  wire _net_126;
-  wire _net_127;
-  wire _net_128;
-  wire _net_129;
-  wire _net_130;
-  wire _net_131;
-  wire _net_132;
-  wire _net_133;
-  wire _net_134;
-  wire _net_135;
-  wire _net_136;
-  wire _net_137;
-  wire _net_138;
-  wire _net_139;
-  wire _net_140;
-  wire _net_141;
-  wire _net_142;
-  wire _net_143;
-  wire _net_144;
-  wire _net_145;
-  wire _net_146;
-  wire _net_147;
-  wire _net_148;
-  wire _net_149;
-  wire _net_150;
-  wire _net_151;
-  wire _net_152;
-  wire _net_153;
-  wire _net_154;
-  wire _net_155;
-  wire _net_156;
-  wire _net_157;
-  wire _net_158;
-  wire _net_159;
-  wire _net_160;
-  wire _net_161;
-  wire _net_162;
-  wire _net_163;
-  wire _net_164;
-  wire _net_165;
-  wire _net_166;
-  wire _net_167;
-  wire _net_168;
-  wire _net_169;
-  wire _net_170;
-  wire _net_171;
-  wire _net_172;
-  wire _net_173;
-  wire _net_174;
-  wire _net_175;
-  wire _net_176;
-  wire _net_177;
-  wire _net_178;
-  wire _net_179;
-  wire _net_180;
-  wire _net_181;
-  wire _net_182;
-  wire _net_183;
-  wire _net_184;
-  wire _net_185;
-  wire _net_186;
-  wire _net_187;
-  wire _net_188;
-  wire _net_189;
-  wire _net_190;
-  wire _net_191;
-  wire _net_192;
-  wire _net_193;
-  wire _net_194;
-  wire _net_195;
-  wire _net_196;
-  wire _net_197;
-  wire _net_198;
-  wire _net_199;
-  wire _net_200;
-  wire _net_201;
-  wire _net_202;
-  wire _net_203;
-  wire _net_204;
-  wire _net_205;
-  wire _net_206;
-  wire _net_207;
-  wire _net_208;
-  wire _net_209;
-  wire _net_210;
-  wire _net_211;
-  wire _net_212;
-  wire _net_213;
-  wire _net_214;
-  wire _net_215;
-  wire _net_216;
-  wire _net_217;
-  wire _net_218;
-
-   assign  fs_disp_data = _net_10;
-   assign  w_red = 4'b0000;
-   assign  w_green = 4'b0000;
-   assign  w_blue = ((_net_20)?4'b0000:4'b0)|
-    ((_net_18)?4'b1111:4'b0);
-   assign  w_disp_data = ((_net_218)?r2[31]:1'b0)|
-    ((_net_215)?r2[30]:1'b0)|
-    ((_net_212)?r2[29]:1'b0)|
-    ((_net_209)?r2[28]:1'b0)|
-    ((_net_206)?r2[27]:1'b0)|
-    ((_net_203)?r2[26]:1'b0)|
-    ((_net_200)?r2[25]:1'b0)|
-    ((_net_197)?r2[24]:1'b0)|
-    ((_net_194)?r2[23]:1'b0)|
-    ((_net_191)?r2[22]:1'b0)|
-    ((_net_188)?r2[21]:1'b0)|
-    ((_net_185)?r2[20]:1'b0)|
-    ((_net_182)?r2[19]:1'b0)|
-    ((_net_179)?r2[18]:1'b0)|
-    ((_net_176)?r2[17]:1'b0)|
-    ((_net_173)?r2[16]:1'b0)|
-    ((_net_170)?r2[15]:1'b0)|
-    ((_net_167)?r2[14]:1'b0)|
-    ((_net_164)?r2[13]:1'b0)|
-    ((_net_161)?r2[12]:1'b0)|
-    ((_net_158)?r2[11]:1'b0)|
-    ((_net_155)?r2[10]:1'b0)|
-    ((_net_152)?r2[9]:1'b0)|
-    ((_net_149)?r2[8]:1'b0)|
-    ((_net_146)?r2[7]:1'b0)|
-    ((_net_143)?r2[6]:1'b0)|
-    ((_net_140)?r2[5]:1'b0)|
-    ((_net_137)?r2[4]:1'b0)|
-    ((_net_134)?r2[3]:1'b0)|
-    ((_net_131)?r2[2]:1'b0)|
-    ((_net_128)?r2[1]:1'b0)|
-    ((_net_124)?r2[0]:1'b0)|
-    ((_net_121)?r1[31]:1'b0)|
-    ((_net_118)?r1[30]:1'b0)|
-    ((_net_115)?r1[29]:1'b0)|
-    ((_net_112)?r1[28]:1'b0)|
-    ((_net_109)?r1[27]:1'b0)|
-    ((_net_106)?r1[26]:1'b0)|
-    ((_net_103)?r1[25]:1'b0)|
-    ((_net_100)?r1[24]:1'b0)|
-    ((_net_97)?r1[23]:1'b0)|
-    ((_net_94)?r1[22]:1'b0)|
-    ((_net_91)?r1[21]:1'b0)|
-    ((_net_88)?r1[20]:1'b0)|
-    ((_net_85)?r1[19]:1'b0)|
-    ((_net_82)?r1[18]:1'b0)|
-    ((_net_79)?r1[17]:1'b0)|
-    ((_net_76)?r1[16]:1'b0)|
-    ((_net_73)?r1[15]:1'b0)|
-    ((_net_70)?r1[14]:1'b0)|
-    ((_net_67)?r1[13]:1'b0)|
-    ((_net_64)?r1[12]:1'b0)|
-    ((_net_61)?r1[11]:1'b0)|
-    ((_net_58)?r1[10]:1'b0)|
-    ((_net_55)?r1[9]:1'b0)|
-    ((_net_52)?r1[8]:1'b0)|
-    ((_net_49)?r1[7]:1'b0)|
-    ((_net_46)?r1[6]:1'b0)|
-    ((_net_43)?r1[5]:1'b0)|
-    ((_net_40)?r1[4]:1'b0)|
-    ((_net_37)?r1[3]:1'b0)|
-    ((_net_34)?r1[2]:1'b0)|
-    ((_net_31)?r1[1]:1'b0)|
-    ((_net_27)?r1[0]:1'b0);
-   assign  _net_0 = (r_h_cnt)==(10'b1100100000);
-   assign  _net_1 = (r_h_cnt)==(10'b1100001110);
-   assign  _net_2 = (r_h_cnt)==(10'b0010001110);
-   assign  _net_3 = (r_h_cnt)==(10'b0001100000);
-   assign  _net_4 = (((~_net_0)&(~_net_1))&(~_net_2))&(~_net_3);
-   assign  _net_5 = (r_v_cnt)==(19'b1100101110000011111);
-   assign  _net_6 = (r_v_cnt)==(19'b1100011110011011111);
-   assign  _net_7 = (r_v_cnt)==(19'b0000110000011011111);
-   assign  _net_8 = (r_v_cnt)==(19'b0000000011000111111);
-   assign  _net_9 = (((~_net_5)&(~_net_6))&(~_net_7))&(~_net_8);
-   assign  _net_10 = r_hdata_flg&r_vdata_flg;
-   assign  _net_11 = (((r_h_cnt) >= ((10'b0010001110)+(10'b1001100001)))&((r_h_cnt) <= (((10'b1100001110)+(10'b1001100001))+(10'b1111111111))))&((r_v_cnt) >= ((19'b0000110000011011111)+(19'b1111111111111100001)))&((r_v_cnt) <= (((19'b1100011110011011111)+(19'b1111111111111100001))+(19'b1111111111111111111)));
-   assign  _net_12 = (r_bit32_cnt)==(5'b00000);
-   assign  _net_13 = _net_11&_net_12;
-   assign  _net_14 = (r_bit32_cnt)==(5'b11111);
-   assign  _net_15 = _net_11&_net_14;
-   assign  _net_16 = _net_11&(~_net_14);
-   assign  _net_17 = ~_net_11;
-   assign  _net_18 = r_hdata_flg&r_vdata_flg;
-   assign  _net_19 = ~_net_18;
-   assign  _net_20 = ~_net_18;
-   assign  _net_21 = ~_net_18;
-   assign  _net_22 = fi_ack_req_32dot&r_data_select_flag;
-   assign  _net_23 = fi_ack_req_32dot&(~r_data_select_flag);
-   assign  _net_24 = ~r_flg;
-   assign  _net_25 = (r_bit32_cnt)==(5'b11111);
-   assign  _net_26 = fs_disp_data&_net_24;
-   assign  _net_27 = (fs_disp_data&_net_24)&_net_25;
-   assign  _net_28 = (fs_disp_data&_net_24)&_net_25;
-   assign  _net_29 = (r_bit32_cnt)==(5'b11110);
-   assign  _net_30 = fs_disp_data&_net_24;
-   assign  _net_31 = (fs_disp_data&_net_24)&_net_29;
-   assign  _net_32 = (r_bit32_cnt)==(5'b11101);
-   assign  _net_33 = fs_disp_data&_net_24;
-   assign  _net_34 = (fs_disp_data&_net_24)&_net_32;
-   assign  _net_35 = (r_bit32_cnt)==(5'b11100);
-   assign  _net_36 = fs_disp_data&_net_24;
-   assign  _net_37 = (fs_disp_data&_net_24)&_net_35;
-   assign  _net_38 = (r_bit32_cnt)==(5'b11011);
-   assign  _net_39 = fs_disp_data&_net_24;
-   assign  _net_40 = (fs_disp_data&_net_24)&_net_38;
-   assign  _net_41 = (r_bit32_cnt)==(5'b11010);
-   assign  _net_42 = fs_disp_data&_net_24;
-   assign  _net_43 = (fs_disp_data&_net_24)&_net_41;
-   assign  _net_44 = (r_bit32_cnt)==(5'b11001);
-   assign  _net_45 = fs_disp_data&_net_24;
-   assign  _net_46 = (fs_disp_data&_net_24)&_net_44;
-   assign  _net_47 = (r_bit32_cnt)==(5'b11000);
-   assign  _net_48 = fs_disp_data&_net_24;
-   assign  _net_49 = (fs_disp_data&_net_24)&_net_47;
-   assign  _net_50 = (r_bit32_cnt)==(5'b10111);
-   assign  _net_51 = fs_disp_data&_net_24;
-   assign  _net_52 = (fs_disp_data&_net_24)&_net_50;
-   assign  _net_53 = (r_bit32_cnt)==(5'b10110);
-   assign  _net_54 = fs_disp_data&_net_24;
-   assign  _net_55 = (fs_disp_data&_net_24)&_net_53;
-   assign  _net_56 = (r_bit32_cnt)==(5'b10101);
-   assign  _net_57 = fs_disp_data&_net_24;
-   assign  _net_58 = (fs_disp_data&_net_24)&_net_56;
-   assign  _net_59 = (r_bit32_cnt)==(5'b10100);
-   assign  _net_60 = fs_disp_data&_net_24;
-   assign  _net_61 = (fs_disp_data&_net_24)&_net_59;
-   assign  _net_62 = (r_bit32_cnt)==(5'b10011);
-   assign  _net_63 = fs_disp_data&_net_24;
-   assign  _net_64 = (fs_disp_data&_net_24)&_net_62;
-   assign  _net_65 = (r_bit32_cnt)==(5'b10010);
-   assign  _net_66 = fs_disp_data&_net_24;
-   assign  _net_67 = (fs_disp_data&_net_24)&_net_65;
-   assign  _net_68 = (r_bit32_cnt)==(5'b10001);
-   assign  _net_69 = fs_disp_data&_net_24;
-   assign  _net_70 = (fs_disp_data&_net_24)&_net_68;
-   assign  _net_71 = (r_bit32_cnt)==(5'b10000);
-   assign  _net_72 = fs_disp_data&_net_24;
-   assign  _net_73 = (fs_disp_data&_net_24)&_net_71;
-   assign  _net_74 = (r_bit32_cnt)==(5'b01111);
-   assign  _net_75 = fs_disp_data&_net_24;
-   assign  _net_76 = (fs_disp_data&_net_24)&_net_74;
-   assign  _net_77 = (r_bit32_cnt)==(5'b01110);
-   assign  _net_78 = fs_disp_data&_net_24;
-   assign  _net_79 = (fs_disp_data&_net_24)&_net_77;
-   assign  _net_80 = (r_bit32_cnt)==(5'b01101);
-   assign  _net_81 = fs_disp_data&_net_24;
-   assign  _net_82 = (fs_disp_data&_net_24)&_net_80;
-   assign  _net_83 = (r_bit32_cnt)==(5'b01100);
-   assign  _net_84 = fs_disp_data&_net_24;
-   assign  _net_85 = (fs_disp_data&_net_24)&_net_83;
-   assign  _net_86 = (r_bit32_cnt)==(5'b01011);
-   assign  _net_87 = fs_disp_data&_net_24;
-   assign  _net_88 = (fs_disp_data&_net_24)&_net_86;
-   assign  _net_89 = (r_bit32_cnt)==(5'b01010);
-   assign  _net_90 = fs_disp_data&_net_24;
-   assign  _net_91 = (fs_disp_data&_net_24)&_net_89;
-   assign  _net_92 = (r_bit32_cnt)==(5'b01001);
-   assign  _net_93 = fs_disp_data&_net_24;
-   assign  _net_94 = (fs_disp_data&_net_24)&_net_92;
-   assign  _net_95 = (r_bit32_cnt)==(5'b01000);
-   assign  _net_96 = fs_disp_data&_net_24;
-   assign  _net_97 = (fs_disp_data&_net_24)&_net_95;
-   assign  _net_98 = (r_bit32_cnt)==(5'b00111);
-   assign  _net_99 = fs_disp_data&_net_24;
-   assign  _net_100 = (fs_disp_data&_net_24)&_net_98;
-   assign  _net_101 = (r_bit32_cnt)==(5'b00110);
-   assign  _net_102 = fs_disp_data&_net_24;
-   assign  _net_103 = (fs_disp_data&_net_24)&_net_101;
-   assign  _net_104 = (r_bit32_cnt)==(5'b00101);
-   assign  _net_105 = fs_disp_data&_net_24;
-   assign  _net_106 = (fs_disp_data&_net_24)&_net_104;
-   assign  _net_107 = (r_bit32_cnt)==(5'b00100);
-   assign  _net_108 = fs_disp_data&_net_24;
-   assign  _net_109 = (fs_disp_data&_net_24)&_net_107;
-   assign  _net_110 = (r_bit32_cnt)==(5'b00011);
-   assign  _net_111 = fs_disp_data&_net_24;
-   assign  _net_112 = (fs_disp_data&_net_24)&_net_110;
-   assign  _net_113 = (r_bit32_cnt)==(5'b00010);
-   assign  _net_114 = fs_disp_data&_net_24;
-   assign  _net_115 = (fs_disp_data&_net_24)&_net_113;
-   assign  _net_116 = (r_bit32_cnt)==(5'b00001);
-   assign  _net_117 = fs_disp_data&_net_24;
-   assign  _net_118 = (fs_disp_data&_net_24)&_net_116;
-   assign  _net_119 = (r_bit32_cnt)==(5'b00000);
-   assign  _net_120 = fs_disp_data&_net_24;
-   assign  _net_121 = (fs_disp_data&_net_24)&_net_119;
-   assign  _net_122 = (r_bit32_cnt)==(5'b11111);
-   assign  _net_123 = fs_disp_data&(~_net_24);
-   assign  _net_124 = (fs_disp_data&(~_net_24))&_net_122;
-   assign  _net_125 = (fs_disp_data&(~_net_24))&_net_122;
-   assign  _net_126 = (r_bit32_cnt)==(5'b11110);
-   assign  _net_127 = fs_disp_data&(~_net_24);
-   assign  _net_128 = (fs_disp_data&(~_net_24))&_net_126;
-   assign  _net_129 = (r_bit32_cnt)==(5'b11101);
-   assign  _net_130 = fs_disp_data&(~_net_24);
-   assign  _net_131 = (fs_disp_data&(~_net_24))&_net_129;
-   assign  _net_132 = (r_bit32_cnt)==(5'b11100);
-   assign  _net_133 = fs_disp_data&(~_net_24);
-   assign  _net_134 = (fs_disp_data&(~_net_24))&_net_132;
-   assign  _net_135 = (r_bit32_cnt)==(5'b11011);
-   assign  _net_136 = fs_disp_data&(~_net_24);
-   assign  _net_137 = (fs_disp_data&(~_net_24))&_net_135;
-   assign  _net_138 = (r_bit32_cnt)==(5'b11010);
-   assign  _net_139 = fs_disp_data&(~_net_24);
-   assign  _net_140 = (fs_disp_data&(~_net_24))&_net_138;
-   assign  _net_141 = (r_bit32_cnt)==(5'b11001);
-   assign  _net_142 = fs_disp_data&(~_net_24);
-   assign  _net_143 = (fs_disp_data&(~_net_24))&_net_141;
-   assign  _net_144 = (r_bit32_cnt)==(5'b11000);
-   assign  _net_145 = fs_disp_data&(~_net_24);
-   assign  _net_146 = (fs_disp_data&(~_net_24))&_net_144;
-   assign  _net_147 = (r_bit32_cnt)==(5'b10111);
-   assign  _net_148 = fs_disp_data&(~_net_24);
-   assign  _net_149 = (fs_disp_data&(~_net_24))&_net_147;
-   assign  _net_150 = (r_bit32_cnt)==(5'b10110);
-   assign  _net_151 = fs_disp_data&(~_net_24);
-   assign  _net_152 = (fs_disp_data&(~_net_24))&_net_150;
-   assign  _net_153 = (r_bit32_cnt)==(5'b10101);
-   assign  _net_154 = fs_disp_data&(~_net_24);
-   assign  _net_155 = (fs_disp_data&(~_net_24))&_net_153;
-   assign  _net_156 = (r_bit32_cnt)==(5'b10100);
-   assign  _net_157 = fs_disp_data&(~_net_24);
-   assign  _net_158 = (fs_disp_data&(~_net_24))&_net_156;
-   assign  _net_159 = (r_bit32_cnt)==(5'b10011);
-   assign  _net_160 = fs_disp_data&(~_net_24);
-   assign  _net_161 = (fs_disp_data&(~_net_24))&_net_159;
-   assign  _net_162 = (r_bit32_cnt)==(5'b10010);
-   assign  _net_163 = fs_disp_data&(~_net_24);
-   assign  _net_164 = (fs_disp_data&(~_net_24))&_net_162;
-   assign  _net_165 = (r_bit32_cnt)==(5'b10001);
-   assign  _net_166 = fs_disp_data&(~_net_24);
-   assign  _net_167 = (fs_disp_data&(~_net_24))&_net_165;
-   assign  _net_168 = (r_bit32_cnt)==(5'b10000);
-   assign  _net_169 = fs_disp_data&(~_net_24);
-   assign  _net_170 = (fs_disp_data&(~_net_24))&_net_168;
-   assign  _net_171 = (r_bit32_cnt)==(5'b01111);
-   assign  _net_172 = fs_disp_data&(~_net_24);
-   assign  _net_173 = (fs_disp_data&(~_net_24))&_net_171;
-   assign  _net_174 = (r_bit32_cnt)==(5'b01110);
-   assign  _net_175 = fs_disp_data&(~_net_24);
-   assign  _net_176 = (fs_disp_data&(~_net_24))&_net_174;
-   assign  _net_177 = (r_bit32_cnt)==(5'b01101);
-   assign  _net_178 = fs_disp_data&(~_net_24);
-   assign  _net_179 = (fs_disp_data&(~_net_24))&_net_177;
-   assign  _net_180 = (r_bit32_cnt)==(5'b01100);
-   assign  _net_181 = fs_disp_data&(~_net_24);
-   assign  _net_182 = (fs_disp_data&(~_net_24))&_net_180;
-   assign  _net_183 = (r_bit32_cnt)==(5'b01011);
-   assign  _net_184 = fs_disp_data&(~_net_24);
-   assign  _net_185 = (fs_disp_data&(~_net_24))&_net_183;
-   assign  _net_186 = (r_bit32_cnt)==(5'b01010);
-   assign  _net_187 = fs_disp_data&(~_net_24);
-   assign  _net_188 = (fs_disp_data&(~_net_24))&_net_186;
-   assign  _net_189 = (r_bit32_cnt)==(5'b01001);
-   assign  _net_190 = fs_disp_data&(~_net_24);
-   assign  _net_191 = (fs_disp_data&(~_net_24))&_net_189;
-   assign  _net_192 = (r_bit32_cnt)==(5'b01000);
-   assign  _net_193 = fs_disp_data&(~_net_24);
-   assign  _net_194 = (fs_disp_data&(~_net_24))&_net_192;
-   assign  _net_195 = (r_bit32_cnt)==(5'b00111);
-   assign  _net_196 = fs_disp_data&(~_net_24);
-   assign  _net_197 = (fs_disp_data&(~_net_24))&_net_195;
-   assign  _net_198 = (r_bit32_cnt)==(5'b00110);
-   assign  _net_199 = fs_disp_data&(~_net_24);
-   assign  _net_200 = (fs_disp_data&(~_net_24))&_net_198;
-   assign  _net_201 = (r_bit32_cnt)==(5'b00101);
-   assign  _net_202 = fs_disp_data&(~_net_24);
-   assign  _net_203 = (fs_disp_data&(~_net_24))&_net_201;
-   assign  _net_204 = (r_bit32_cnt)==(5'b00100);
-   assign  _net_205 = fs_disp_data&(~_net_24);
-   assign  _net_206 = (fs_disp_data&(~_net_24))&_net_204;
-   assign  _net_207 = (r_bit32_cnt)==(5'b00011);
-   assign  _net_208 = fs_disp_data&(~_net_24);
-   assign  _net_209 = (fs_disp_data&(~_net_24))&_net_207;
-   assign  _net_210 = (r_bit32_cnt)==(5'b00010);
-   assign  _net_211 = fs_disp_data&(~_net_24);
-   assign  _net_212 = (fs_disp_data&(~_net_24))&_net_210;
-   assign  _net_213 = (r_bit32_cnt)==(5'b00001);
-   assign  _net_214 = fs_disp_data&(~_net_24);
-   assign  _net_215 = (fs_disp_data&(~_net_24))&_net_213;
-   assign  _net_216 = (r_bit32_cnt)==(5'b00000);
-   assign  _net_217 = fs_disp_data&(~_net_24);
-   assign  _net_218 = (fs_disp_data&(~_net_24))&_net_216;
-   assign  o_v_sync = r_v_sync;
-   assign  o_h_sync = r_h_sync;
-   assign  o_vga_red = w_red;
-   assign  o_vga_green = w_green;
-   assign  o_vga_blue = w_blue;
-   assign  o_h_cnt = r_h_cnt;
-   assign  fo_req_32dot = _net_13;
-always @(posedge m_clock or posedge p_reset)
-  begin
-if (p_reset)
-     r_v_sync <= 1'b0;
-else if ((_net_8|_net_5)) 
-      r_v_sync <= ~r_v_sync;
-end
-always @(posedge m_clock or posedge p_reset)
-  begin
-if (p_reset)
-     r_h_sync <= 1'b0;
-else if ((_net_3|_net_0)) 
-      r_h_sync <= ~r_h_sync;
-end
-always @(posedge p_reset)
- begin
-if (p_reset)
-     r_h_flg <= 1'b0;
-end
-always @(posedge m_clock or posedge p_reset)
-  begin
-if (p_reset)
-     r_vdata_flg <= 1'b0;
-else if ((_net_7)|(_net_6)) 
-      r_vdata_flg <= ((_net_7) ?1'b1:1'b0)|
-    ((_net_6) ?1'b0:1'b0);
-
-end
-always @(posedge m_clock or posedge p_reset)
-  begin
-if (p_reset)
-     r_hdata_flg <= 1'b0;
-else if ((_net_2)|(_net_1)) 
-      r_hdata_flg <= ((_net_2) ?1'b1:1'b0)|
-    ((_net_1) ?1'b0:1'b0);
-
-end
-always @(posedge m_clock or posedge p_reset)
-  begin
-if (p_reset)
-     r_h_cnt <= 10'b0000000000;
-else if ((_net_4|_net_3|_net_2|_net_1)|(_net_0)) 
-      r_h_cnt <= ((_net_4|_net_3|_net_2|_net_1) ?(r_h_cnt)+(10'b0000000001):10'b0)|
-    ((_net_0) ?10'b0000000000:10'b0);
-
-end
-always @(posedge m_clock or posedge p_reset)
-  begin
-if (p_reset)
-     r_v_cnt <= 19'b0000000000000000000;
-else if ((_net_9|_net_8|_net_7|_net_6)|(_net_5)) 
-      r_v_cnt <= ((_net_9|_net_8|_net_7|_net_6) ?(r_v_cnt)+(19'b0000000000000000001):19'b0)|
-    ((_net_5) ?19'b0000000000000000000:19'b0);
-
-end
-always @(posedge m_clock or posedge p_reset)
-  begin
-if (p_reset)
-     r_bit32_cnt <= 5'b00000;
-else if ((fs_disp_data)|(_net_16)|(_net_17|_net_15)) 
-      r_bit32_cnt <= ((fs_disp_data) ?(r_bit32_cnt)+(5'b00001):5'b0)|
-    ((_net_16) ?(r_bit32_cnt)+(5'b00001):5'b0)|
-    ((_net_17|_net_15) ?5'b00000:5'b0);
-
-end
-always @(posedge m_clock or posedge p_reset)
-  begin
-if (p_reset)
-     r_flg <= 1'b0;
-else if ((_net_125|_net_28)) 
-      r_flg <= ~r_flg;
-end
-always @(posedge p_reset)
- begin
-if (p_reset)
-     r_cnt <= 1'b0;
-end
-always @(posedge m_clock or posedge p_reset)
-  begin
-if (p_reset)
-     r1 <= 32'b00000000000000000000000000000000;
-else if ((_net_22)) 
-      r1 <= i_pix32_data;
-end
-always @(posedge m_clock or posedge p_reset)
-  begin
-if (p_reset)
-     r2 <= 32'b00000000000000000000000000000000;
-else if ((_net_23)) 
-      r2 <= i_pix32_data;
-end
-always @(posedge m_clock or posedge p_reset)
-  begin
-if (p_reset)
-     r_data_select_flag <= 1'b0;
-else if ((fi_ack_req_32dot)) 
-      r_data_select_flag <= ~r_data_select_flag;
-end
-endmodule
-/*
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Fri Jul 08 20:38:20 2011
- Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp 
-*/
diff --git a/VGADisplay/Verilog/vga_top.v b/VGADisplay/Verilog/vga_top.v
index 0addb68..9a1b10e 100644
--- a/VGADisplay/Verilog/vga_top.v
+++ b/VGADisplay/Verilog/vga_top.v
@@ -1,9 +1,16 @@
 /*
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Fri Jul 08 20:39:37 2011
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Mon Jul 11 14:01:02 2011
  Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER:
 */
 
-module vga_generate ( p_reset , m_clock , i_pix32_data , o_v_sync , o_h_sync , o_vga_red , o_vga_green , o_vga_blue , o_h_cnt , fi_ack_req_32dot , fo_req_32dot );
+module vga_generate ( i_50clk , i_we1 , i_wadrs1 , i_wdata1 , i_we2 , i_wadrs2 , i_wdata2 , p_reset , m_clock , i_pix32_data , o_v_sync , o_h_sync , o_vga_red , o_vga_green , o_vga_blue , o_h_cnt , fi_ack_req_32dot , fo_req_32dot );
+  input i_50clk;
+  input i_we1;
+  input [4:0] i_wadrs1;
+  input [31:0] i_wdata1;
+  input i_we2;
+  input [4:0] i_wadrs2;
+  input [31:0] i_wdata2;
   input p_reset;
   input m_clock;
   input [31:0] i_pix32_data;
@@ -16,6 +23,7 @@ module vga_generate ( p_reset , m_clock , i_pix32_data , o_v_sync , o_h_sync , o
   input fi_ack_req_32dot;
   output fo_req_32dot;
   wire fs_disp_data;
+  reg r_line_buff_cnt;
   reg r_v_sync;
   reg r_h_sync;
   reg r_h_flg;
@@ -33,6 +41,19 @@ module vga_generate ( p_reset , m_clock , i_pix32_data , o_v_sync , o_h_sync , o
   wire [3:0] w_green;
   wire [3:0] w_blue;
   wire w_disp_data;
+  wire _u_FIFO_p_reset;
+  wire _u_FIFO_m_clock;
+  wire _u_FIFO_i_we1;
+  wire [6:0] _u_FIFO_i_wadrs1;
+  wire [7:0] _u_FIFO_i_wdata1;
+  wire _u_FIFO_i_we2;
+  wire [6:0] _u_FIFO_i_wadrs2;
+  wire [7:0] _u_FIFO_i_wdata2;
+  wire [6:0] _u_FIFO_i_radrs1;
+  wire [7:0] _u_FIFO_o_rdasrs1;
+  wire [6:0] _u_FIFO_i_radrs2;
+  wire [7:0] _u_FIFO_o_rdasrs2;
+  wire _u_FIFO_i_clock;
   wire _net_0;
   wire _net_1;
   wire _net_2;
@@ -252,6 +273,7 @@ module vga_generate ( p_reset , m_clock , i_pix32_data , o_v_sync , o_h_sync , o
   wire _net_216;
   wire _net_217;
   wire _net_218;
+FIFO u_FIFO (.i_clock(_u_FIFO_i_clock), .o_rdasrs2(_u_FIFO_o_rdasrs2), .i_radrs2(_u_FIFO_i_radrs2), .o_rdasrs1(_u_FIFO_o_rdasrs1), .i_radrs1(_u_FIFO_i_radrs1), .i_wdata2(_u_FIFO_i_wdata2), .i_wadrs2(_u_FIFO_i_wadrs2), .i_we2(_u_FIFO_i_we2), .i_wdata1(_u_FIFO_i_wdata1), .i_wadrs1(_u_FIFO_i_wadrs1), .i_we1(_u_FIFO_i_we1), .m_clock(_u_FIFO_m_clock), .p_reset(_u_FIFO_p_reset));
 
    assign  fs_disp_data = _net_10;
    assign  w_red = 4'b0000;
@@ -548,6 +570,11 @@ module vga_generate ( p_reset , m_clock , i_pix32_data , o_v_sync , o_h_sync , o
    assign  o_vga_blue = w_blue;
    assign  o_h_cnt = r_h_cnt;
    assign  fo_req_32dot = _net_13;
+always @(posedge p_reset)
+ begin
+if (p_reset)
+     r_line_buff_cnt <= 1'b0;
+end
 always @(posedge m_clock or posedge p_reset)
   begin
 if (p_reset)
@@ -648,6 +675,6 @@ else if ((fi_ack_req_32dot))
 end
 endmodule
 /*
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Fri Jul 08 20:39:41 2011
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Mon Jul 11 14:01:06 2011
  Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp 
 */
diff --git a/VGADisplay/src/vga_generate.nsh b/VGADisplay/src/vga_generate.nsh
index f903d83..59fa65b 100644
--- a/VGADisplay/src/vga_generate.nsh
+++ b/VGADisplay/src/vga_generate.nsh
@@ -1,4 +1,12 @@
 declare vga_generate interface {
+	input  i_50clk ;
+	input  i_we1 ;
+	input  i_wadrs1[5] ;
+	input  i_wdata1[32] ;
+	input  i_we2 ;
+	input  i_wadrs2[5] ;
+	input  i_wdata2[32] ;
+
 	input  p_reset ;
 	input  m_clock ;
 	input  i_pix32_data[32] ;
diff --git a/VGADisplay/src/vga_generate.nsl b/VGADisplay/src/vga_generate.nsl
index 3f17a66..852eaf4 100644
--- a/VGADisplay/src/vga_generate.nsl
+++ b/VGADisplay/src/vga_generate.nsl
@@ -1,6 +1,6 @@
-//%d CNT_H_00			0b0000000000
+//%d CNT_H_00		0b0000000000
 //%d CNT_H1			0b0001011111 /* 96clock */
-//%d CNT_H_REP32		0b0001101110 /* 110 clock */
+//%d CNT_H_REP32	0b0001101110 /* 110 clock */
 //%d CNT_H_DATA_IN	0b0010001110 /* 142 for 144clock */
 //%d CNT_H_DATA_OUT	0b1100001110 /* 782 for 784clock */
 //%d CNT_H2			0b1100011111 /* 800clock */
@@ -14,6 +14,8 @@
 //%d CNT_V_DATA_OUT	0b1100011110011011111 /* 408800clock */ 
 //%d CNT_V2			0b1100101110000011111 /* 416800clock */
 
+#include "vga_ram.nsh"
+
 /**
 *	VGA@Signal Generate Circuit
 *	Module name is "vga_generate"
@@ -43,6 +45,15 @@
 
 
 declare vga_generate  interface {
+	// FIFO@interface
+	input  i_50clk ;
+	input  i_we1 ;
+	input  i_wadrs1[5] ;
+	input  i_wdata1[32] ;
+	input  i_we2 ;
+	input  i_wadrs2[5] ;
+	input  i_wdata2[32] ;
+
 	input  p_reset ;
 	input  m_clock ;
 	input  i_pix32_data[32] ;
@@ -55,11 +66,15 @@ declare vga_generate  interface {
 
 	func_in  fi_ack_req_32dot(i_pix32_data) ;
 	func_out fo_req_32dot ;
+	
+	func_in vgaram_write1() ;
+	func_in vgaram_write2() ;
 }
-
 module vga_generate {
 	func_self fs_disp_data ;
 
+	reg r_line_buff_cnt = 0 ;
+
 	reg r_v_sync = 0 ;
 	reg r_h_sync = 0 ;
 	reg r_h_flg = 0 ;
@@ -81,16 +96,48 @@ module vga_generate {
 	wire w_green[4] ;
 	wire w_blue[4] ;
 	wire w_disp_data;
+	
+	reg r_rptr1[5] = 0 ;
+	reg r_rptr2[5] = 0 ;
+	reg r_wptr1[5] = 0 ;
+	reg r_wptr2[5] = 0 ;
+	reg r_cnt_hsync[10] = 0 ;
+	reg r_cnt_flg = 0 ;
+	reg r_hld_h_sync = 0 ;
+
+	func_self vgaram_read1() ;
+	func_self vgaram_read2() ;
+
+	func_self vgaram_reset1() ;
+	func_self vgaram_reset2() ;
+
+	vga_ram u_VGARAM ;
 
 	{
-		o_v_sync	= r_v_sync;
-		o_h_sync	= r_h_sync;
-		o_vga_red	= w_red;
-		o_vga_green	= w_green;
-		o_vga_blue  = w_blue;
-		o_h_cnt		= r_h_cnt;
+		o_v_sync	= r_v_sync ;
+		o_h_sync	= r_h_sync ;
+		o_vga_red	= w_red ;
+		o_vga_green	= w_green ;
+		o_vga_blue  = w_blue ;
+		o_h_cnt		= r_h_cnt ;
 
 
+		/* y point counter */
+		r_h_sync := r_hld_h_sync ;
+
+		if( r_v_sync ) {
+			if(r_h_sync & ~r_hld_h_sync) {
+				if(~r_cnt_flg) {
+					r_cnt_flg := 1 ;
+				} else {
+					r_cnt_hsync++ ;
+				}
+			}
+		} else {
+			r_cnt_flg := 0 ;
+			r_cnt_hsync := 0 ;
+		}
+
 		//horizonal synchronous signal generate
 		any{
 			r_h_cnt == 10'd96 : {
@@ -270,5 +317,5 @@ module vga_generate {
 			}
 		}
 		r_bit32_cnt++ ;
-	}//disp_data
-}//module end
+	} //disp_data
+} //module end
\ No newline at end of file
diff --git a/VGADisplay/src/FIFO.nsh b/VGADisplay/src/vga_ram.nsh
similarity index 90%
rename from VGADisplay/src/FIFO.nsh
rename to VGADisplay/src/vga_ram.nsh
index c571607..5394cde 100644
--- a/VGADisplay/src/FIFO.nsh
+++ b/VGADisplay/src/vga_ram.nsh
@@ -1,4 +1,4 @@
-declare FIFO interface {
+declare vga_ram interface {
 	input p_reset ;
 	input m_clock ;
 	
diff --git a/VGADisplay/src/FIFO.v b/VGADisplay/src/vga_ram.v
similarity index 54%
rename from VGADisplay/src/FIFO.v
rename to VGADisplay/src/vga_ram.v
index 24c6cbf..c82156f 100644
--- a/VGADisplay/src/FIFO.v
+++ b/VGADisplay/src/vga_ram.v
@@ -1,4 +1,4 @@
-module FIFO (
+module vga_ram (
 	p_reset, m_clock, i_we1,
 	i_wadrs1, i_wdata1, i_we2,
 	i_wadrs2, i_wdata2, i_radrs1,
@@ -10,25 +10,25 @@ module FIFO (
 	input m_clock ;
 	
 	input i_we1 ;
-	input [6:0] i_wadrs1 ;
-	input [7:0] i_wdata1 ;
+	input [4:0] i_wadrs1 ;
+	input [31:0] i_wdata1 ;
 
 	input i_clock ;
 	input i_we2 ;
-	input [6:0] i_wadrs2 ;
-	input [7:0] i_wdata2 ;
+	input [4:0] i_wadrs2 ;
+	input [31:0] i_wdata2 ;
 	
-	input  [6:0] i_radrs1 ;
-	output [7:0] o_rdasrs1 ;
+	input  [4:0] i_radrs1 ;
+	output [31:0] o_rdasrs1 ;
 
-	input  [6:0] i_radrs2 ;
-	output [7:0] o_rdasrs2 ;
+	input  [4:0] i_radrs2 ;
+	output [31:0] o_rdasrs2 ;
 
-	reg [6:0] r_rdadrs1 ;
-	reg [6:0] r_rdadrs2 ;
+	reg [4:0] r_rdadrs1 ;
+	reg [4:0] r_rdadrs2 ;
 	
-	(* remstyle = "no_rw_check" *) reg [7:0] mem1[127:0] ;
-	(* remstyle = "no_rw_check" *) reg [7:0] mem2[127:0] ;
+	(* remstyle = "no_rw_check" *) reg [31:0] mem1[31:0] ;
+	(* remstyle = "no_rw_check" *) reg [31:0] mem2[31:0] ;
 	
 	// memory write command
 	always @ (posedge m_clock) begin
diff --git a/VGADisplay/src/vga_top.nsl b/VGADisplay/src/vga_top.nsl
index efc2f98..df9c723 100644
--- a/VGADisplay/src/vga_top.nsl
+++ b/VGADisplay/src/vga_top.nsl
@@ -16,7 +16,9 @@
 //#define ONE_SEC 25'd100
 
 
-declare vga_top {
+declare vga_top interface {
+	input  p_reset ;
+	input  m_clock ;
 	output o_v_sync ;
 	output o_h_sync ;
 	output o_red[4] ;
@@ -43,13 +45,12 @@ module vga_top {
 
 	vga_generate u_VGA ;
 	exp_ctrl	 u_EXP ;
-	FIFO		 u_FIFO ;
 	
-//	o_v_sync	= u_VGA.o_v_sync ;
-//	o_h_sync	= u_VGA.o_h_sync ;
-//	o_red		= u_VGA.o_vga_red ;
-//	o_green		= u_VGA.o_vga_green ;
-//	o_blue		= u_VGA.o_vga_blue ;
+	o_v_sync	= u_VGA.o_v_sync ;
+	o_h_sync	= u_VGA.o_h_sync ;
+	o_red		= u_VGA.o_vga_red ;
+	o_green		= u_VGA.o_vga_green ;
+	o_blue		= u_VGA.o_vga_blue ;
 
 	if( u_VGA.fo_req_32dot ) {
 		u_VGA.fi_ack_req_32dot( 32'hFFFFFFFF ) ;
-- 
2.11.0