From a9d2e3ed4ddbef4f56a007dc6a04509e828cd98f Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 12 Apr 2023 13:43:31 +0200 Subject: [PATCH] target/riscv: Merge checks for reserved pte flags Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-24-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-24-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 9a2b944990..c7c384bae3 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -962,14 +962,14 @@ restart: /* Reserved without Svpbmt. */ return TRANSLATE_FAIL; } - if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) { - /* Reserved leaf PTE flags: PTE_W */ - return TRANSLATE_FAIL; - } - if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) { - /* Reserved leaf PTE flags: PTE_W + PTE_X */ + + /* Check for reserved combinations of RWX flags. */ + switch (pte & (PTE_R | PTE_W | PTE_X)) { + case PTE_W: + case PTE_W | PTE_X: return TRANSLATE_FAIL; } + if ((pte & PTE_U) && ((mode != PRV_U) && (!sum || access_type == MMU_INST_FETCH))) { /* -- 2.11.0