From a9fe5d8c63ef742f3253c1cc802f217d5dd901bd Mon Sep 17 00:00:00 2001
From: astoria-d <astoria-d@mail.goo.ne.jp>
Date: Mon, 17 Jun 2013 01:24:16 +0900
Subject: [PATCH] all code re-write.

---
 simulation/cpu/cpu_registers.vhd | 666 +++++++--------------------------------
 simulation/cpu/decoder.vhd       | 660 +++++---------------------------------
 simulation/cpu/mos6502.vhd       | 608 ++++++++++-------------------------
 3 files changed, 374 insertions(+), 1560 deletions(-)

diff --git a/simulation/cpu/cpu_registers.vhd b/simulation/cpu/cpu_registers.vhd
index b2426cd..0c56f26 100644
--- a/simulation/cpu/cpu_registers.vhd
+++ b/simulation/cpu/cpu_registers.vhd
@@ -1,167 +1,44 @@
 
 ----------------------------------------
---- program counter register declaration
+--- d-flipflop with set/reset
 ----------------------------------------
 
 library ieee;
 use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.std_logic_arith.conv_std_logic_vector;
 
-entity pc is 
-    generic (
-            dsize : integer := 8;
-            reset_addr : integer := 0
-            );
-    port (  
-            clk             : in std_logic;
-            res_n           : in std_logic;
-            pc_type         : in std_logic;     --'0' pcl, '1' pch
-            dbus_we_n       : in std_logic;
-            abus_we_n       : in std_logic;
-            dbus_oe_n       : in std_logic;
-            abus_oe_n       : in std_logic;
-            addr_inc_n      : in std_logic;
-            addr_dec_n      : in std_logic;
-            add_carry       : out std_logic;
-            rel_we_n        : in std_logic;
-            rel_calc_n      : in std_logic;
-            rel_prev        : out std_logic;
-            int_d_bus       : inout std_logic_vector (dsize - 1 downto 0);
-            int_a_bus       : inout std_logic_vector (dsize - 1 downto 0)
-        );
-end pc;
-
-architecture rtl of pc is
-
-component dff
-    generic (
-            dsize : integer := 8
-            );
-    port (  
-            clk         : in std_logic;
-            we_n    : in std_logic;
-            oe_n    : in std_logic;
-            d       : in std_logic_vector (dsize - 1 downto 0);
-            q       : out std_logic_vector (dsize - 1 downto 0)
-        );
-end component;
-
-signal val : std_logic_vector (dsize - 1 downto 0);
-signal rel : std_logic_vector (dsize - 1 downto 0);
-
-begin
-                ---increment & page moved case.
-    int_a_bus <= val + 1 when (abus_oe_n = '0' 
-                                and pc_type = '1' and addr_inc_n = '0') else
-                val when (abus_oe_n = '0') else
-                (others => 'Z');
-
-                ---increment & page moved case.
-    int_d_bus <= val + 1 when (dbus_oe_n = '0' 
-                                and pc_type = '1' and addr_inc_n = '0') else
-                val when (dbus_oe_n = '0') else
-                (others => 'Z');
-
-    set_p : process (clk, res_n)
-    variable add_val : std_logic_vector(dsize downto 0);
-    variable dec_val : std_logic_vector(dsize downto 0);
-    begin
-        if (clk'event and clk = '1') then
-
-            if (addr_inc_n = '0' and abus_we_n = '0') then
-                --case increment & address set
-                --for jmp op, abs xy not page crossing case.
-                add_val := ('0' & int_a_bus) + 1;
-                val <= add_val(dsize - 1 downto 0);
-                add_carry <= add_val(dsize);
-                rel_prev <= '0';
-            elsif (addr_inc_n = '0') then
-                add_val := ('0' & val) + 1;
-                val <= add_val(dsize - 1 downto 0);
-                add_carry <= add_val(dsize);
-                rel_prev <= '0';
-            elsif (addr_dec_n = '0') then
-                dec_val := ('0' & val) - 1;
-                val <= dec_val(dsize - 1 downto 0);
-                add_carry <= '0';
-                rel_prev <= '0';
-            elsif (rel_calc_n = '0') then
-                add_val := ('0' & val) + ('0' & rel);
-                --relative addressing mode is signed operation.
-                if (rel(7) = '0') then
-                    --add positive
-                    add_carry <= add_val(dsize);
-                    rel_prev <= '0';
-                else
-                    --add negative
-                    add_carry <= '0';
-                    if (add_val(7) = '1') then
-                        --negative value > goto preveous page.
-                        rel_prev <= '1';
-                    else
-                        rel_prev <= '0';
-                    end if;
-                end if;
-                val <= add_val(dsize - 1 downto 0);
-            elsif (abus_we_n = '0') then
-                val <= int_a_bus;
-                add_carry <= '0';
-                rel_prev <= '0';
-            elsif (dbus_we_n = '0') then
-                val <= int_d_bus;
-                add_carry <= '0';
-                rel_prev <= '0';
-            else
-                rel_prev <= '0';
-                add_carry <= '0';
-            end if;
-        elsif (res_n'event and res_n = '0') then
-            val <= conv_std_logic_vector(reset_addr, dsize);
-        end if;
-    end process;
-
-    rel_dff : dff generic map (dsize) 
-                    port map(clk, rel_we_n, '0', int_d_bus, rel);
-end rtl;
-
-----------------------------------------
---- normal d-flipflop declaration
-----------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity dff is 
+entity d_flip_flop is 
     generic (
             dsize : integer := 8
             );
     port (  
             clk     : in std_logic;
+            res_n   : in std_logic;
+            set_n   : in std_logic;
             we_n    : in std_logic;
-            oe_n    : in std_logic;
             d       : in std_logic_vector (dsize - 1 downto 0);
             q       : out std_logic_vector (dsize - 1 downto 0)
         );
-end dff;
+end d_flip_flop;
 
-architecture rtl of dff is
-signal val : std_logic_vector (dsize - 1 downto 0);
+architecture rtl of d_flip_flop is
 begin
 
-    process (clk)
+    process (clk, res_n, set_n)
     begin
-        if ( clk'event and clk = '1'and we_n = '0') then
-            val <= d;
+        if (res_n = '0') then
+            q <= (others => '0');
+        elsif (clk'event and clk = '1' and set_n = '0') then
+            q <= d;
+        elsif (clk'event and clk = '1') then
+            if (we_n = '0') then
+                q <= d;
+            end if;
         end if;
     end process;
-
-    q <= val when oe_n = '0' else
-        (others => 'Z');
 end rtl;
 
 ----------------------------------------
---- normal data latch declaration
+--- data latch declaration
 ----------------------------------------
 
 library ieee;
@@ -173,553 +50,242 @@ entity latch is
             );
     port (  
             clk     : in std_logic;
-            oe_n    : in std_logic;
             d       : in std_logic_vector (dsize - 1 downto 0);
             q       : out std_logic_vector (dsize - 1 downto 0)
         );
 end latch;
 
 architecture rtl of latch is
-signal val : std_logic_vector (dsize - 1 downto 0);
 begin
 
     process (clk, d)
     begin
         if ( clk = '1') then
             --latch only when clock is high
-            val <= d;
+            q <= d;
         end if;
     end process;
-
-    q <= val when oe_n = '0' else
-        (others => 'Z');
 end rtl;
 
 ----------------------------------------
---- data bus buffer register
+--- tri-state buffer
 ----------------------------------------
 
 library ieee;
 use ieee.std_logic_1164.all;
 
-entity dbus_buf is 
-    generic (
-            dsize : integer := 8
-            );
-    port (  
-            clk         : in std_logic;
-            r_nw        : in std_logic;
-            int_oe_n    : in std_logic;
-            int_dbus : inout std_logic_vector (dsize - 1 downto 0);
-            ext_dbus : inout std_logic_vector (dsize - 1 downto 0)
-        );
-end dbus_buf;
-
-architecture rtl of dbus_buf is
-component latch
+entity tri_state_buffer is 
     generic (
             dsize : integer := 8
             );
     port (  
-            clk     : in std_logic;
             oe_n    : in std_logic;
             d       : in std_logic_vector (dsize - 1 downto 0);
             q       : out std_logic_vector (dsize - 1 downto 0)
         );
-end component;
+end tri_state_buffer;
 
-signal rd_clk : std_logic;
-signal wr_clk : std_logic;
+architecture rtl of tri_state_buffer is
 begin
-    rd_clk <= r_nw and clk;
-    wr_clk <= (not r_nw) and clk;
-
-    --read from i/o to cpu
-    latch_r : latch generic map (dsize) 
-                    port map(rd_clk, int_oe_n, ext_dbus, int_dbus);
-    --write from cpu to io
-    latch_w : latch generic map (dsize) 
-                    port map(wr_clk, r_nw, int_dbus, ext_dbus);
+    q <= d when oe_n = '0' else
+        (others => 'Z');
 end rtl;
 
+
 ----------------------------------------
---- input data latch register
+--- dual port d flip flop w/ tri-state buffer
 ----------------------------------------
 
 library ieee;
 use ieee.std_logic_1164.all;
 
-entity input_dl is 
+entity dual_dff is 
     generic (
             dsize : integer := 8
             );
     port (  
-            clk         : in std_logic;
-            al_we_n     : in std_logic;
-            ah_we_n     : in std_logic;
-            al_oe_n     : in std_logic;
-            ah_oe_n     : in std_logic;
-            int_dbus    : in std_logic_vector (dsize - 1 downto 0);
-            ea_al       : out std_logic_vector (dsize - 1 downto 0);
-            ea_ah       : out std_logic_vector (dsize - 1 downto 0)
+            clk             : in std_logic;
+            res_n           : in std_logic;
+            set_n           : in std_logic;
+            gate_cmd        : in std_logic_vector (3 downto 0);
+            front_port      : inout std_logic_vector (dsize - 1 downto 0);
+            back_in_port    : in std_logic_vector (dsize - 1 downto 0);
+            back_out_port   : out std_logic_vector (dsize - 1 downto 0)
         );
-end input_dl;
+end dual_dff;
 
-architecture rtl of input_dl is
-component latch
+architecture rtl of dual_dff is
+
+component d_flip_flop
     generic (
             dsize : integer := 8
             );
     port (  
             clk     : in std_logic;
-            oe_n    : in std_logic;
+            res_n   : in std_logic;
+            set_n   : in std_logic;
+            we_n    : in std_logic;
             d       : in std_logic_vector (dsize - 1 downto 0);
             q       : out std_logic_vector (dsize - 1 downto 0)
         );
 end component;
-signal ll_clk : std_logic;
-signal lh_clk : std_logic;
-signal ql : std_logic_vector (dsize - 1 downto 0);
-signal qh : std_logic_vector (dsize - 1 downto 0);
-begin
-
-    ll_clk <= (not al_we_n) and clk;
-    lh_clk <= (not ah_we_n) and clk;
-    latch_l : latch generic map (dsize) 
-                    port map(ll_clk, '0', int_dbus, ql);
-    latch_h : latch generic map (dsize) 
-                    port map(lh_clk, '0', int_dbus, qh);
-
-    --tri-state buffer at the output
-    ea_al <= ql when al_oe_n = '0' else
-         (others =>'Z');
-    ea_ah <= qh when ah_oe_n = '0' else
-         (others =>'Z');
 
-end rtl;
-
-----------------------------------------
---- stack pointer register
-----------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-
-entity sp is 
-    generic (
-            dsize : integer := 8
-            );
-    port (  
-            clk         : in std_logic;
-            we_n        : in std_logic;
-            push_n      : in std_logic;
-            pop_n       : in std_logic;
-            int_d_oe_n  : in std_logic;
-            int_a_oe_n  : in std_logic;
-            int_dbus    : inout std_logic_vector (dsize - 1 downto 0);
-            int_abus_l  : out std_logic_vector (dsize - 1 downto 0);
-            int_abus_h  : out std_logic_vector (dsize - 1 downto 0)
-        );
-end sp;
-
-architecture rtl of sp is
-component dff
+component tri_state_buffer
     generic (
             dsize : integer := 8
             );
     port (  
-            clk         : in std_logic;
-            we_n    : in std_logic;
             oe_n    : in std_logic;
             d       : in std_logic_vector (dsize - 1 downto 0);
             q       : out std_logic_vector (dsize - 1 downto 0)
         );
 end component;
-signal oe_n : std_logic;
-signal dff_we_n : std_logic;
+
+signal we_n : std_logic;
 signal q : std_logic_vector (dsize - 1 downto 0);
 signal d : std_logic_vector (dsize - 1 downto 0);
-signal q_buf : std_logic_vector (dsize - 1 downto 0);
 
 begin
-    oe_n <= (int_d_oe_n and int_a_oe_n);
-    dff_we_n <= (we_n and push_n and pop_n);
-    int_dbus <= q when int_d_oe_n = '0' else
-         (others =>'Z');
-
-    ---push: address decrement after push is done.
-    ---pop: address increment before pop is done.
-    al_p : process (int_a_oe_n, push_n, clk, q_buf, q)
-    begin
-        if (int_a_oe_n = '0') then
-            if (push_n = '0') then
-                if (clk = '1') then
-                    int_abus_l <= q_buf;
-                else
-                    int_abus_l <= q;
-                end if;
-            elsif (pop_n = '0') then
-                if (clk = '1') then
-                    int_abus_l <= q_buf;
-                else
-                    int_abus_l <= q;
-                end if;
-            else
-                int_abus_l <= q;
-            end if;
-        else
-            int_abus_l <= (others => 'Z');
-        end if;
-    end process;
+    ----------gate_cmd format 
+    ------3 : front port oe_n
+    ------2 : front port we_n
+    ------1 : back port oe_n
+    ------0 : back port we_n
+    we_n <= (gate_cmd(2) and gate_cmd(0));
 
-    int_abus_h <= "00000001" when int_a_oe_n = '0' else
-         (others =>'Z');
-    d <= int_dbus when we_n = '0' else
-            (q - 1) when push_n = '0' else
-            (q + 1) when pop_n = '0' else
-         (others =>'Z');
-
-    dff_inst : dff generic map (dsize) 
-                    port map(clk, dff_we_n, oe_n, d, q);
-    buf : dff generic map (dsize) 
-                    port map(clk, dff_we_n, '0', q, q_buf);
-end rtl;
-
-
-----------------------------------------
---- SR flipflop
-----------------------------------------
+    d <= front_port when gate_cmd(2) = '0' else
+         back_in_port when gate_cmd(0) = '0' else
+         (others => 'Z');
 
-library ieee;
-use ieee.std_logic_1164.all;
+    dff_inst : d_flip_flop generic map (dsize) 
+                    port map(clk, res_n, set_n, we_n, d, q);
 
-entity srff is 
-    generic (
-            dsize : integer := 8
-            );
-    port (  
-            clk     : in std_logic;
-            res_n   : in std_logic;
-            set_n   : in std_logic;
-            we_n    : in std_logic;
-            oe_n    : in std_logic;
-            d       : in std_logic_vector (dsize - 1 downto 0);
-            q       : out std_logic_vector (dsize - 1 downto 0)
-        );
-end srff;
+    front_tsb : tri_state_buffer generic map (dsize) 
+                    port map(gate_cmd(3), q, front_port);
 
-architecture rtl of srff is
-signal val : std_logic_vector (dsize - 1 downto 0);
-begin
+    back_tsb : tri_state_buffer generic map (dsize) 
+                    port map(gate_cmd(1), q, back_out_port);
+end rtl;
 
-    q <= val when oe_n = '0' else
-        (others => 'Z');
 
-    main_p : process (clk, res_n, set_n, d)
-    begin
-        if ( clk'event and clk = '1'and we_n = '0') then
-            val <= d;
-        end if;
-        if (res_n'event and res_n = '0') then
-            val <= (others => '0');
-        end if;
-        if (set_n = '0') then
-            val <= d;
-        end if;
-    end process;
-end rtl;
+-----------------
 
 ----------------------------------------
---- status register component
+--- data bus buffer
 ----------------------------------------
 
 library ieee;
 use ieee.std_logic_1164.all;
 
-entity processor_status is 
+entity data_bus_buffer is 
     generic (
             dsize : integer := 8
             );
     port (  
             clk         : in std_logic;
-            res_n       : in std_logic;
-            dec_oe_n    : in std_logic;
-            bus_oe_n    : in std_logic;
-            set_flg_n   : in std_logic;
-            flg_val     : in std_logic;
-            load_bus_all_n : in std_logic;
-            load_bus_nz_n  : in std_logic;
-            alu_we_n    : in std_logic;
-            alu_n       : in std_logic;
-            alu_v       : in std_logic;
-            alu_z       : in std_logic;
-            alu_c       : in std_logic;
-            decoder     : inout std_logic_vector (dsize - 1 downto 0);
-            int_dbus    : inout std_logic_vector (dsize - 1 downto 0)
+            r_nw        : in std_logic;
+            int_oe_n    : in std_logic;
+            int_dbus : inout std_logic_vector (dsize - 1 downto 0);
+            ext_dbus : inout std_logic_vector (dsize - 1 downto 0)
         );
-end processor_status;
+end data_bus_buffer;
 
-architecture rtl of processor_status is
-signal val : std_logic_vector (dsize - 1 downto 0);
-begin
-    decoder <= val when dec_oe_n = '0' else
-                (others => 'Z');
-    int_dbus <= val when bus_oe_n = '0' else
-                (others => 'Z');
-                
-
-    main_p : process (clk, res_n)
-    variable tmp : std_logic_vector (dsize - 1 downto 0);
-    begin
---        SR Flags (bit 7 to bit 0):
---
---        N   ....    Negative
---        V   ....    Overflow
---        -   ....    ignored
---        B   ....    Break
---        D   ....    Decimal (use BCD for arithmetics)
---        I   ....    Interrupt (IRQ disable)
---        Z   ....    Zero
---        C   ....    Carry
-    
-      ---only interrupt flag is set on reset.
-        if (res_n'event and res_n = '0') then
-            val <= "00000100";
-        end if;
-
-        if ( clk'event and clk = '1') then
-            ---from flag set/clear instructions
-            if (set_flg_n = '0') then
-                if flg_val = '1' then
-                    tmp := (decoder and "11111111");
-                else
-                    tmp := "00000000";
-                end if;
-                val <= tmp or (val and not decoder);
-
-            ---status flag set from the data on the internal data bus.
-            ---interpret the input data by the decoder input.
-            ---load/pop/rti/t[asxy]
-            elsif (load_bus_all_n = '0') then
-                ---set the data bus data as they are.
-                val <= int_dbus;
-            elsif (load_bus_nz_n = '0') then
-                ---other case: n/z data must be interpreted.
-                --n bit.
-                if int_dbus(7) = '1' then
-                    val (7) <= '1';
-                else
-                    val (7) <= '0';
-                end if;
-                --z bit.
-                ---nor outputs 1 when all inputs are 0.
-                if  (int_dbus(7) or int_dbus(6) or 
-                        int_dbus(5) or int_dbus(4) or int_dbus(3) or 
-                        int_dbus(2) or int_dbus(1) or int_dbus(0)) = '0' then
-                    val (1) <= '1';
-                else
-                    val (1) <= '0';
-                end if;
-
-            ---status set from alu/inx/iny etc.
-            elsif (alu_we_n = '0') then
-                tmp := val;
-                val (5 downto 2) <= tmp (5 downto 2);
-
-                --n bit.
-                if (decoder(7) = '1') then
-                    val (7) <= alu_n;
-                else
-                    val (7) <= tmp (7);
-                end if;
-                --v bit.
-                if (decoder(6) = '1') then
-                    val (6) <= alu_v;
-                else
-                    val (6) <= tmp (6);
-                end if;
-                --z bit.
-                if (decoder(1) = '1') then
-                    val (1) <= alu_z;
-                else
-                    val (1) <= tmp (1);
-                end if;
-                --c bit.
-                if (decoder(0) = '1') then
-                    val (0) <= alu_c;
-                else
-                    val (0) <= tmp (0);
-                end if;
-            end if; --if (set_flg_n = '0') then
-        end if;
-    end process;
-end rtl;
-
-
-----------------------------------------
---- tri-state buffer
-----------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity tsb is 
+architecture rtl of data_bus_buffer is
+component latch
     generic (
             dsize : integer := 8
             );
     port (  
-            oe_n    : in std_logic;
+            clk     : in std_logic;
             d       : in std_logic_vector (dsize - 1 downto 0);
             q       : out std_logic_vector (dsize - 1 downto 0)
         );
-end tsb;
-
-architecture rtl of tsb is
-signal val : std_logic_vector (dsize - 1 downto 0);
-begin
-    q <= d when oe_n = '0' else
-        (others => 'Z');
-end rtl;
-
-
-----------------------------------------
---- accumulator
-----------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity accumulator is 
-    generic (
-            dsize : integer := 8
-            );
-    port (  
-            clk         : in std_logic;
-            d_we_n      : in std_logic;
-            alu_we_n    : in std_logic;
-            d_oe_n      : in std_logic;
-            int_dbus    : inout std_logic_vector (dsize - 1 downto 0);
-            alu_out     : in std_logic_vector (dsize - 1 downto 0);
-            alu_in      : out std_logic_vector (dsize - 1 downto 0)
-        );
-end accumulator;
+end component;
 
-architecture rtl of accumulator is
-component dff
+component tri_state_buffer
     generic (
             dsize : integer := 8
             );
     port (  
-            clk     : in std_logic;
-            we_n    : in std_logic;
             oe_n    : in std_logic;
             d       : in std_logic_vector (dsize - 1 downto 0);
             q       : out std_logic_vector (dsize - 1 downto 0)
         );
 end component;
 
-signal we_n : std_logic;
-signal d : std_logic_vector (dsize - 1 downto 0);
-signal q : std_logic_vector (dsize - 1 downto 0);
-
+signal rd_clk : std_logic;
+signal wr_clk : std_logic;
+signal read_buf : std_logic_vector (dsize - 1 downto 0);
+signal write_buf : std_logic_vector (dsize - 1 downto 0);
 begin
-    we_n <= (d_we_n and alu_we_n);
-    d <= int_dbus when d_we_n = '0' else
-        alu_out when alu_we_n = '0' else
-        (others => 'Z');
-    int_dbus <= q when d_oe_n = '0' else
-        (others => 'Z');
-    alu_in <= q;
+    rd_clk <= r_nw and clk;
+    wr_clk <= (not r_nw) and clk;
 
     --read from i/o to cpu
-    dff_inst : dff generic map (dsize) 
-                    port map(clk, we_n, '0', d, q);
+    latch_r : latch generic map (dsize) 
+                    port map(rd_clk, ext_dbus, read_buf);
+    read_tsb : tri_state_buffer generic map (dsize) 
+                    port map(int_oe_n, read_buf, int_dbus);
+    --write from cpu to io
+    latch_w : latch generic map (dsize) 
+                    port map(wr_clk, int_dbus, write_buf);
+    write_tsb : tri_state_buffer generic map (dsize) 
+                    port map(r_nw, write_buf, ext_dbus);
 end rtl;
 
-----------------------------------------
---- index register x/y
-----------------------------------------
+------------------------------------------
+----- input data latch register
+------------------------------------------
 
 library ieee;
 use ieee.std_logic_1164.all;
 
-entity index_reg is 
+entity input_data_latch is 
     generic (
             dsize : integer := 8
             );
     port (  
             clk         : in std_logic;
-            d_we_n      : in std_logic;
-            d_oe_n      : in std_logic;
-            ea_oe_n     : in std_logic;
-            inc_n       : in std_logic;
-            dec_n       : in std_logic;
-            int_dbus    : inout std_logic_vector (dsize - 1 downto 0);
-            ea_bus      : out std_logic_vector (dsize - 1 downto 0);
-            n           : out std_logic;
-            z           : out std_logic
+            oe_n        : in std_logic;
+            we_n        : in std_logic;
+            int_dbus    : in std_logic_vector (dsize - 1 downto 0);
+            alu_bus     : out std_logic_vector (dsize - 1 downto 0)
         );
-end index_reg;
+end input_data_latch;
 
-architecture rtl of index_reg is
-component dff
+architecture rtl of input_data_latch is
+
+component latch
     generic (
             dsize : integer := 8
             );
     port (  
             clk     : in std_logic;
-            we_n    : in std_logic;
-            oe_n    : in std_logic;
             d       : in std_logic_vector (dsize - 1 downto 0);
             q       : out std_logic_vector (dsize - 1 downto 0)
         );
 end component;
 
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
+component tri_state_buffer
+    generic (
+            dsize : integer := 8
+            );
+    port (  
+            oe_n    : in std_logic;
+            d       : in std_logic_vector (dsize - 1 downto 0);
+            q       : out std_logic_vector (dsize - 1 downto 0)
+        );
+end component;
 
-signal we_n : std_logic;
-signal q : std_logic_vector (dsize - 1 downto 0);
-signal d : std_logic_vector (dsize - 1 downto 0);
+signal latch_clk : std_logic;
+signal latch_buf : std_logic_vector (dsize - 1 downto 0);
 
 begin
-    int_dbus <= q when d_oe_n = '0' else
-        (others => 'Z');
-    ea_bus <= q when ea_oe_n = '0' else
-        (others => 'Z');
-
-    --for inx/iny/dex/dey instructions...
-    inc_dec_p : process (clk, int_dbus, inc_n, dec_n)
-    variable inc_work : std_logic_vector (dsize downto 0);
-    variable dec_work : std_logic_vector (dsize downto 0);
-    begin
-        inc_work := ('0' & q) + 1;
-        dec_work := ('0' & q) - 1;
-        if inc_n = '0' then
-            d <= inc_work(dsize - 1 downto 0);
-            z <= not (inc_work(7) or inc_work(6) or 
-                    inc_work(5) or inc_work(4) or inc_work(3) or 
-                    inc_work(2) or inc_work(1) or inc_work(0));
-            n <= inc_work(dsize);
-        elsif dec_n = '0' then
-            d <= dec_work(dsize - 1 downto 0);
-            z <= not (dec_work(7) or dec_work(6) or 
-                dec_work(5) or dec_work(4) or dec_work(3) or 
-                dec_work(2) or dec_work(1) or dec_work(0)); 
-            n <= dec_work(dsize); 
-        else
-            d <= int_dbus;
-            z <= 'Z';
-            n <= 'Z';
-        end if;
-
-    end process;
-
-    --read from i/o to cpu
-    we_n <= d_we_n and inc_n and dec_n;
-    dff_inst : dff generic map (dsize) 
-                    port map(clk, we_n, '0', d, q);
+    latch_clk <= (not we_n) and clk;
+    latch_inst : latch generic map (dsize) 
+                    port map(latch_clk, int_dbus, latch_buf);
+    iput_data_tsb : tri_state_buffer generic map (dsize) 
+                    port map(oe_n, latch_buf, alu_bus);
 
 end rtl;
 
diff --git a/simulation/cpu/decoder.vhd b/simulation/cpu/decoder.vhd
index 5fdd54e..4c163e8 100644
--- a/simulation/cpu/decoder.vhd
+++ b/simulation/cpu/decoder.vhd
@@ -12,58 +12,17 @@ entity decoder is
             nmi_n           : in std_logic;
             rdy             : in std_logic;
             instruction     : in std_logic_vector (dsize - 1 downto 0);
-            exec_cycle      : in std_logic_vector (4 downto 0);
-            next_cycle      : out std_logic_vector (4 downto 0);
+            exec_cycle      : in std_logic_vector (5 downto 0);
+            next_cycle      : out std_logic_vector (5 downto 0);
             status_reg      : inout std_logic_vector (dsize - 1 downto 0);
             inst_we_n       : out std_logic;
-            alu_en_n        : out std_logic;
             ad_oe_n         : out std_logic;
-            pcl_inc_n       : out std_logic;
-            pcl_d_we_n      : out std_logic;
-            pcl_a_we_n      : out std_logic;
-            pcl_d_oe_n      : out std_logic;
-            pcl_a_oe_n      : out std_logic;
-            pcl_rel_we_n    : out std_logic;
-            pcl_rel_calc_n  : out std_logic;
-            pch_d_we_n      : out std_logic;
-            pch_a_we_n      : out std_logic;
-            pch_d_oe_n      : out std_logic;
-            pch_a_oe_n      : out std_logic;
-            rel_pg_crs_n    : in std_logic;
-            dbuf_int_oe_n   : out std_logic;
-            dl_al_we_n      : out std_logic;
-            dl_ah_we_n      : out std_logic;
-            dl_al_oe_n      : out std_logic;
-            dl_ah_oe_n      : out std_logic;
-            sp_we_n         : out std_logic;
-            sp_push_n       : out std_logic;
-            sp_pop_n        : out std_logic;
-            sp_int_d_oe_n   : out std_logic;
-            sp_int_a_oe_n   : out std_logic;
-            acc_d_we_n      : out std_logic;
-            acc_alu_we_n    : out std_logic;
-            acc_d_oe_n      : out std_logic;
-            x_we_n          : out std_logic;
-            x_oe_n          : out std_logic;
-            x_ea_oe_n       : out std_logic;
-            x_inc_n         : out std_logic;
-            x_dec_n         : out std_logic;
-            y_we_n          : out std_logic;
-            y_oe_n          : out std_logic;
-            y_ea_oe_n       : out std_logic;
-            y_inc_n         : out std_logic;
-            y_dec_n         : out std_logic;
-            ea_calc_n       : out std_logic;
-            ea_zp_n         : out std_logic;
-            ea_pg_next_n    : out std_logic;
-            ea_carry        : in  std_logic;
-            stat_dec_oe_n   : out std_logic;
-            stat_bus_oe_n   : out std_logic;
-            stat_set_flg_n  : out std_logic;
-            stat_flg        : out std_logic;
-            stat_bus_all_n  : out std_logic;
-            stat_bus_nz_n   : out std_logic;
-            stat_alu_we_n   : out std_logic;
+            pcl_cmd         : out std_logic_vector(3 downto 0);
+            pch_cmd         : out std_logic_vector(3 downto 0);
+            sp_cmd          : out std_logic_vector(3 downto 0);
+            acc_cmd         : out std_logic_vector(3 downto 0);
+            x_cmd           : out std_logic_vector(3 downto 0);
+            y_cmd           : out std_logic_vector(3 downto 0);
             r_nw            : out std_logic
             ;---for parameter check purpose!!!
             check_bit     : out std_logic_vector(1 to 5)
@@ -81,40 +40,7 @@ begin
     writeline(output, out_l);
 end  procedure;
 
-procedure d_print(msg : string; sig : std_logic_vector) is
-use std.textio.all;
-use ieee.std_logic_textio.all;
-variable out_l : line;
-begin
-    write(out_l, msg);
-    write(out_l, sig);
-    writeline(output, out_l);
-end  procedure;
-
-procedure d_print(msg : string; ival : integer) is
-use std.textio.all;
-use ieee.std_logic_textio.all;
-variable out_l : line;
-begin
-    write(out_l, msg);
-    write(out_l, ival);
-    writeline(output, out_l);
-end  procedure;
-
 ---ival : 0x0000 - 0xffff
-function conv_hex16(ival : integer) return string is
-variable tmp1, tmp2, tmp3, tmp4 : integer;
---variable ret : string (1 to 4) := "0000";
-variable hex_chr: string (1 to 16) := "0123456789abcdef";
-begin
-    tmp4 := ival / 16 ** 3;
-    tmp3 := (ival mod 16 ** 3) / 16 ** 2;
-    tmp2 := (ival mod 16 ** 2) / 16 ** 1;
-    tmp1 := ival mod 16 ** 1;
-    return hex_chr(tmp4 + 1) & hex_chr(tmp3 + 1) 
-        & hex_chr(tmp2 + 1) & hex_chr(tmp1 + 1);
-end;
-
 function conv_hex8(ival : integer) return string is
 variable tmp1, tmp2 : integer;
 variable hex_chr: string (1 to 16) := "0123456789abcdef";
@@ -126,40 +52,40 @@ end;
 
 --cycle bit format
 --00xxx : exec cycle : T0 > T1 > T2 > T3 > T4 > T5 > T6 > T7 > T0
-constant T0 : std_logic_vector (4 downto 0) := "00000";
-constant T1 : std_logic_vector (4 downto 0) := "00001";
-constant T2 : std_logic_vector (4 downto 0) := "00010";
-constant T3 : std_logic_vector (4 downto 0) := "00011";
-constant T4 : std_logic_vector (4 downto 0) := "00100";
-constant T5 : std_logic_vector (4 downto 0) := "00101";
-constant T6 : std_logic_vector (4 downto 0) := "00110";
-constant T7 : std_logic_vector (4 downto 0) := "00111";
+constant T0 : std_logic_vector (5 downto 0) := "-00000";
+constant T1 : std_logic_vector (5 downto 0) := "-00001";
+constant T2 : std_logic_vector (5 downto 0) := "-00010";
+constant T3 : std_logic_vector (5 downto 0) := "-00011";
+constant T4 : std_logic_vector (5 downto 0) := "-00100";
+constant T5 : std_logic_vector (5 downto 0) := "-00101";
+constant T6 : std_logic_vector (5 downto 0) := "-00110";
+constant T7 : std_logic_vector (5 downto 0) := "-00111";
 
 --01xxx : reset cycle : R0 > R1 > R2 > R3 > R4 > R5 > T0
-constant R0 : std_logic_vector (4 downto 0) := "01000";
-constant R1 : std_logic_vector (4 downto 0) := "01001";
-constant R2 : std_logic_vector (4 downto 0) := "01010";
-constant R3 : std_logic_vector (4 downto 0) := "01011";
-constant R4 : std_logic_vector (4 downto 0) := "01100";
-constant R5 : std_logic_vector (4 downto 0) := "01101";
+constant R0 : std_logic_vector (5 downto 0) := "-01000";
+constant R1 : std_logic_vector (5 downto 0) := "-01001";
+constant R2 : std_logic_vector (5 downto 0) := "-01010";
+constant R3 : std_logic_vector (5 downto 0) := "-01011";
+constant R4 : std_logic_vector (5 downto 0) := "-01100";
+constant R5 : std_logic_vector (5 downto 0) := "-01101";
 
 --10xxx : nmi cycle : N0 > N1 > N2 > N3 > N4 > N5 > T0
-constant N0 : std_logic_vector (4 downto 0) := "10000";
-constant N1 : std_logic_vector (4 downto 0) := "10001";
-constant N2 : std_logic_vector (4 downto 0) := "10010";
-constant N3 : std_logic_vector (4 downto 0) := "10011";
-constant N4 : std_logic_vector (4 downto 0) := "10100";
-constant N5 : std_logic_vector (4 downto 0) := "10101";
+constant N0 : std_logic_vector (5 downto 0) := "-10000";
+constant N1 : std_logic_vector (5 downto 0) := "-10001";
+constant N2 : std_logic_vector (5 downto 0) := "-10010";
+constant N3 : std_logic_vector (5 downto 0) := "-10011";
+constant N4 : std_logic_vector (5 downto 0) := "-10100";
+constant N5 : std_logic_vector (5 downto 0) := "-10101";
 
 --11xxx : irq cycle : I0 > I1 > I2 > I3 > I4 > I5 > T0
-constant I0 : std_logic_vector (4 downto 0) := "11000";
-constant I1 : std_logic_vector (4 downto 0) := "11001";
-constant I2 : std_logic_vector (4 downto 0) := "11010";
-constant I3 : std_logic_vector (4 downto 0) := "11011";
-constant I4 : std_logic_vector (4 downto 0) := "11100";
-constant I5 : std_logic_vector (4 downto 0) := "11101";
+constant I0 : std_logic_vector (5 downto 0) := "-11000";
+constant I1 : std_logic_vector (5 downto 0) := "-11001";
+constant I2 : std_logic_vector (5 downto 0) := "-11010";
+constant I3 : std_logic_vector (5 downto 0) := "-11011";
+constant I4 : std_logic_vector (5 downto 0) := "-11100";
+constant I5 : std_logic_vector (5 downto 0) := "-11101";
 
-constant ERROR_CYCLE : std_logic_vector (4 downto 0) := "11111";
+constant ERROR_CYCLE : std_logic_vector (5 downto 0) := "111111";
 
 -- SR Flags (bit 7 to bit 0):
 --  7   N   ....    Negative
@@ -180,220 +106,110 @@ constant st_C : integer := 0;
 
 begin
 
-    main_p : process (set_clk, trig_clk, res_n)
+    main_p : process (set_clk, res_n)
 
 -------------------------------------------------------------
 -------------------------------------------------------------
--------------------- comon routine fucntions ----------------
+----------------------- comon routines ----------------------
 -------------------------------------------------------------
 -------------------------------------------------------------
 
+----------gate_cmd format
+------3 : front port oe_n
+------2 : front port we_n
+------1 : back port oe_n
+------0 : back port we_n
+procedure front_oe (signal cmd : out std_logic_vector(3 downto 0); 
+    val : in std_logic) is
+begin
+    cmd(3) <= val;
+end;
+procedure front_we (signal cmd : out std_logic_vector(3 downto 0); 
+    val : in std_logic) is
+begin
+    cmd(2) <= val;
+end;
+procedure back_oe (signal cmd : out std_logic_vector(3 downto 0); 
+    val : in std_logic) is
+begin
+    cmd(1) <= val;
+end;
+procedure back_we (signal cmd : out std_logic_vector(3 downto 0); 
+    val : in std_logic) is
+begin
+    cmd(0) <= val;
+end;
+
 procedure fetch_inst is
 begin
-    d_print(string'("fetch 1"));
     ad_oe_n <= '0';
-    pcl_a_oe_n <= '0';
-    pch_a_oe_n <= '0';
     inst_we_n <= '0';
-    pcl_inc_n <= '0';
-
-    --disable the last opration pins.
-    alu_en_n <= '1';
-    x_oe_n <= '1';
-    y_oe_n <= '1';
-    x_we_n <= '1';
-    y_we_n <= '1';
-    sp_we_n <= '1';
-    sp_push_n <= '1';
-    sp_pop_n <= '1';
+    back_oe(pcl_cmd, '0');
+    back_oe(pch_cmd, '0');
     r_nw <= '1';
-    dbuf_int_oe_n <= '1';
-    pch_d_we_n <= '1';
-    pcl_a_we_n <= '1';
-    pcl_rel_we_n <= '1';
-    pcl_rel_calc_n <= '1';
-    dl_al_we_n <= '1';
-    dl_al_oe_n <= '1';
-    dl_ah_oe_n <= '1';
-    pcl_d_we_n <= '1';
-    pch_a_we_n <= '1';
-    acc_d_we_n <= '1';
-    acc_d_oe_n  <= '1';
-    stat_bus_nz_n <= '1';
-    stat_set_flg_n <= '1';
-    stat_alu_we_n <= '1';
-    x_ea_oe_n <= '1';
-    ea_calc_n <= '1';
-    ea_pg_next_n <= '1';
-    ea_zp_n <= '1';
-    x_inc_n <= '1';
-    x_dec_n <= '1';
-    y_inc_n <= '1';
-    y_dec_n <= '1';
+    --pcl_inc_n <= '0';
+
+    d_print(string'("fetch 1"));
 end;
 
 ---common routine for single byte instruction.
 procedure single_inst is
 begin
-    pcl_a_oe_n <= '1';
-    pch_a_oe_n <= '1';
-    pcl_inc_n <= '1';
-    next_cycle <= T0;
 end  procedure;
 
 procedure fetch_imm is
 begin
     d_print("immediate");
-    pcl_a_oe_n <= '0';
-    pch_a_oe_n <= '0';
-    pcl_inc_n <= '0';
-    --send data from data bus buffer.
-    --receiver is instruction dependent.
-    dbuf_int_oe_n <= '0';
-    next_cycle <= T0;
 end  procedure;
 
 procedure set_nz_from_bus is
 begin
-    --status register n/z bit update.
-    stat_dec_oe_n <= '1';
-    status_reg <= "10000010";
-    stat_bus_nz_n <= '0';
 end  procedure;
 
 procedure set_nz_from_alu is
 begin
-    --status register n/z bit update.
-    stat_alu_we_n <= '0';
-    stat_dec_oe_n <= '1';
-    status_reg <= "10000010";
 end  procedure;
 
 procedure set_nzc_from_alu is
 begin
-    --status register n/z/c bit update.
-    stat_alu_we_n <= '0';
-    stat_dec_oe_n <= '1';
-    status_reg <= "10000011";
 end  procedure;
 
 --flag on/off instruction
 procedure set_flag (int_flg : in integer; val : in std_logic) is
 begin
-    stat_dec_oe_n <= '1';
-    stat_set_flg_n <= '0';
-    --specify which to set.
-    status_reg(7 downto int_flg + 1) 
-        <= (others =>'0');
-    status_reg(int_flg - 1 downto 0) 
-        <= (others =>'0');
-    status_reg(int_flg) <= '1';
-    stat_flg <= val;
 end  procedure;
 
 --for sec/clc
 procedure set_flag0 (val : in std_logic) is
 begin
-    stat_dec_oe_n <= '1';
-    stat_set_flg_n <= '0';
-    status_reg <= "00000001";
-    stat_flg <= val;
 end  procedure;
 
 procedure fetch_low is
 begin
     d_print("fetch low 2");
-    --fetch next opcode (abs low).
-    pcl_a_oe_n <= '0';
-    pch_a_oe_n <= '0';
-    pcl_inc_n <= '0';
-    --latch abs low data.
-    dbuf_int_oe_n <= '0';
-    dl_al_we_n <= '0';
-    next_cycle <= T2;
 end  procedure;
 
 procedure abs_fetch_high is
 begin
     d_print("abs (xy) 3");
-    dl_al_we_n <= '1';
-
-    --latch abs hi data.
-    pcl_inc_n <= '0';
-    pcl_a_oe_n <= '0';
-    pch_a_oe_n <= '0';
-    dbuf_int_oe_n <= '0';
-    dl_ah_we_n <= '0';
-    next_cycle <= T3;
 end  procedure;
 
 procedure abs_latch_out is
 begin
-    --d_print("abs 4");
-    pcl_inc_n <= '1';
-    pcl_a_oe_n <= '1';
-    pch_a_oe_n <= '1';
-    dl_ah_we_n <= '1';
-
-    --latch > al/ah.
-    dl_al_oe_n <= '0';
-    dl_ah_oe_n <= '0';
 end  procedure;
 
 procedure ea_x_out is
 begin
     -----calucurate and output effective addr
-    x_ea_oe_n <= '0';
-    dl_al_oe_n <= '0';
-    dl_ah_oe_n <= '0';
-    ea_calc_n <= '0';
 end  procedure;
 
 --A.2. internal execution on memory data
 procedure a2_abs is
 begin
-    if exec_cycle = T1 then
-        fetch_low;
-    elsif exec_cycle = T2 then
-        abs_fetch_high;
-    elsif exec_cycle = T3 then
-        abs_latch_out;
-        dbuf_int_oe_n <= '0';
-        next_cycle <= T0;
-    end if;
 end  procedure;
 
 procedure a2_absx is
 begin
-    if exec_cycle = T1 then
-        fetch_low;
-    elsif exec_cycle = T2 then
-        abs_fetch_high;
-    elsif exec_cycle = T3 then
-        --ea calc & lda
-        abs_latch_out;
-        ea_x_out;
-        dbuf_int_oe_n <= '0';
-        --instruction specific operation wriiten in the caller position.
-        next_cycle <= T4;
-    elsif exec_cycle = T4 then
-        if ea_carry = '1' then
-            --case page boundary crossed.
-            d_print("absx 5 (page boudary crossed.)");
-            abs_latch_out;
-            ea_x_out;
-            dbuf_int_oe_n <= '0';
-            --next page.
-            ea_pg_next_n <= '0';
-            --redo inst.
-            next_cycle <= T0;
-        else
-            --case page boundary not crossed. do the fetch op.
-            d_print("absx 5 (fetch)");
-            fetch_inst;
-            next_cycle <= T1;
-        end if;
-    end if;
 end  procedure;
 
 
@@ -401,84 +217,16 @@ end  procedure;
 
 procedure a3_zp is
 begin
-    if exec_cycle = T1 then
-        fetch_low;
-    elsif exec_cycle = T2 then
-        pcl_a_oe_n <= '1';
-        pch_a_oe_n <= '1';
-        pcl_inc_n <= '1';
-        dbuf_int_oe_n <= '1';
-        dl_al_we_n <= '1';
-
-        --calc zp.
-        dl_al_oe_n <= '0';
-        ea_zp_n <= '0';
-        r_nw <= '0';
-        next_cycle <= T0;
-    end if;
 end  procedure;
 
 procedure a3_abs is
 begin
-    if exec_cycle = T1 then
-        fetch_low;
-    elsif exec_cycle = T2 then
-        abs_fetch_high;
-    elsif exec_cycle = T3 then
-        abs_latch_out;
-        dbuf_int_oe_n <= '1';
-        r_nw <= '0';
-        next_cycle <= T0;
-    end if;
 end  procedure;
 
 
 -- A.5.8 branch operations
 procedure a58_branch (int_flg : in integer; br_cond : in std_logic) is
 begin
-    if exec_cycle = T1 then
-        stat_dec_oe_n <= '0';
-        pcl_inc_n <= '0';
-        if status_reg(int_flg) = br_cond then
-            d_print("get rel");
-
-            pcl_a_oe_n <= '0';
-            pch_a_oe_n <= '0';
-            dbuf_int_oe_n <= '0';
-            --latch rel value.
-            pcl_rel_we_n <= '0';
-            next_cycle <= T2;
-        else
-            d_print("no branch");
-            next_cycle <= T0;
-        end if;
-    elsif exec_cycle = T2 then
-        d_print("rel ea");
-        pcl_inc_n <= '1';
-        pcl_a_oe_n <= '0';
-        pch_a_oe_n <= '0';
-        dbuf_int_oe_n <= '1';
-        pcl_rel_we_n <= '1';
-
-        --calcurate relative addr.
-        pcl_rel_calc_n <= '0';
-        next_cycle <= T3;
-    elsif exec_cycle = T3 then
-        --pcl_a_oe_n <= '0';
-        --pch_a_oe_n <= '0';
-        pcl_rel_calc_n <= '1';
-
-        if rel_pg_crs_n = '0' then
-        --page crossed. start from fetch.
-            next_cycle <= T0;
-        else
-            --no page boundary. 
-            --fetch cycle is done.
-            fetch_inst;
-            next_cycle <= T1;
-        end if;
-    end if;
-
 end  procedure;
 
 -------------------------------------------------------------
@@ -489,7 +237,13 @@ end  procedure;
     begin
 
         if (res_n = '0') then
+            --pc l/h is reset vector.
+            pcl_cmd <= "1110";
+            pch_cmd <= "1011";
             next_cycle <= R0;
+        elsif (res_n'event and res_n = '1') then
+            pcl_cmd <= "1111";
+            pch_cmd <= "1111";
         end if;
 
         if (set_clk'event and set_clk = '1' and res_n = '1') then
@@ -498,11 +252,7 @@ end  procedure;
             if exec_cycle = T0 then
                 --cycle #1
                 fetch_inst;
-                next_cycle <= T1;
-
-                ---for debug....
-                status_reg <= (others => 'Z');
-                stat_dec_oe_n <= '0';
+                --next_cycle <= T1;
 
             elsif exec_cycle = T1 or exec_cycle = T2 or exec_cycle = T3 or 
                 exec_cycle = T4 or exec_cycle = T5 or exec_cycle = T6 or 
@@ -512,12 +262,6 @@ end  procedure;
                 if exec_cycle = T1 then
                     d_print("decode and execute inst: " 
                             & conv_hex8(conv_integer(instruction)));
-                    --disable pin for jmp/abs [xy] page boundary case.
-                    dl_al_oe_n <= '1';
-                    dl_ah_oe_n <= '1';
-                    pcl_a_we_n <= '1';
-                    pch_a_we_n <= '1';
-
                     --grab instruction register data.
                     inst_we_n <= '1';
                 end if;
@@ -551,21 +295,18 @@ end  procedure;
 
                 elsif instruction = conv_std_logic_vector(16#ca#, dsize) then
                     d_print("dex");
-                    x_dec_n <= '0';
                     --set nz bit.
                     set_nz_from_alu ;
                     single_inst;
 
                 elsif instruction = conv_std_logic_vector(16#88#, dsize) then
                     d_print("dey");
-                    y_dec_n <= '0';
                     --set nz bit.
                     set_nz_from_alu ;
                     single_inst;
 
                 elsif instruction = conv_std_logic_vector(16#e8#, dsize) then
                     d_print("inx");
-                    x_inc_n <= '0';
                     --set nz bit.
                     set_nz_from_alu ;
                     single_inst;
@@ -617,8 +358,6 @@ end  procedure;
 
                 elsif instruction = conv_std_logic_vector(16#9a#, dsize) then
                     d_print("txs");
-                    sp_we_n <= '0';
-                    x_oe_n <= '0';
                     set_nz_from_bus;
                     single_inst;
 
@@ -707,7 +446,6 @@ end  procedure;
                     --imm
                     d_print("cmp");
                     fetch_imm;
-                    alu_en_n <= '0';
                     set_nzc_from_alu;
 
                 elsif instruction  = conv_std_logic_vector(16#c5#, dsize) then
@@ -798,7 +536,6 @@ end  procedure;
                     --imm
                     d_print("lda");
                     fetch_imm;
-                    acc_d_we_n <= '0';
                     set_nz_from_bus;
 
                 elsif instruction  = conv_std_logic_vector(16#a5#, dsize) then
@@ -814,7 +551,6 @@ end  procedure;
                     d_print("lda");
                     a2_abs;
                     if exec_cycle = T3 then
-                        acc_d_we_n  <= '0';
                         set_nz_from_bus;
                     end if;
 
@@ -824,14 +560,8 @@ end  procedure;
                     a2_absx;
                     if exec_cycle = T3 then
                         --lda.
-                        acc_d_we_n  <= '0';
                         set_nz_from_bus;
                     elsif exec_cycle = T4 then
-                        if ea_carry = '1' then
-                            --redo lda
-                            acc_d_we_n  <= '0';
-                            set_nz_from_bus;
-                        end if;
                     end if;
 
                 elsif instruction  = conv_std_logic_vector(16#b9#, dsize) then
@@ -850,7 +580,6 @@ end  procedure;
                     --imm
                     d_print("ldx");
                     fetch_imm;
-                    x_we_n <= '0';
                     set_nz_from_bus;
 
                 elsif instruction  = conv_std_logic_vector(16#a6#, dsize) then
@@ -873,7 +602,6 @@ end  procedure;
                     --imm
                     d_print("ldy");
                     fetch_imm;
-                    y_we_n <= '0';
                     set_nz_from_bus;
 
                 elsif instruction  = conv_std_logic_vector(16#a4#, dsize) then
@@ -966,7 +694,6 @@ end  procedure;
                     d_print("sta");
                     a3_zp;
                     if exec_cycle = T2 then
-                        acc_d_oe_n  <= '0';
                     end if;
 
                 elsif instruction  = conv_std_logic_vector(16#95#, dsize) then
@@ -978,31 +705,11 @@ end  procedure;
                     d_print("sta");
                     a3_abs;
                     if exec_cycle = T3 then
-                        acc_d_oe_n  <= '0';
                     end if;
 
                 elsif instruction  = conv_std_logic_vector(16#9d#, dsize) then
                     --abs, x
                     d_print("sta");
-                    --TODO re-check !!!!
---                    if exec_cycle = T1 then
---                        fetch_low;
---                    elsif exec_cycle = T2 then
---                        abs_fetch_high;
---                    elsif exec_cycle = T3 then
---                        abs_latch_out;
---                        ea_x_out;
---                        next_cycle <= T4;
---                    elsif exec_cycle = T4 then
---                        abs_latch_out;
---                        dbuf_int_oe_n <= '1';
---                        ea_x_out;
---                        ea_pg_next_n <= not ea_carry;
---                        --sta
---                        r_nw <= '0';
---                        acc_d_oe_n  <= '0';
---                        next_cycle <= T0;
---                    end if;
 
                 elsif instruction  = conv_std_logic_vector(16#99#, dsize) then
                     --abs, y
@@ -1021,7 +728,6 @@ end  procedure;
                     d_print("stx");
                     a3_zp;
                     if exec_cycle = T2 then
-                        x_oe_n  <= '0';
                     end if;
 
                 elsif instruction  = conv_std_logic_vector(16#96#, dsize) then
@@ -1167,74 +873,6 @@ end  procedure;
                 -- A.5.3 jsr
                 ----------------------------------------
                 elsif instruction = conv_std_logic_vector(16#20#, dsize) then
-                    if exec_cycle = T1 then
-                        d_print("jsr abs 2");
-                        --fetch opcode.
-                        pcl_a_oe_n <= '0';
-                        pch_a_oe_n <= '0';
-                        pcl_inc_n <= '0';
-                        dbuf_int_oe_n <= '0';
-                        --latch adl
-                        dl_al_we_n <= '0';
-                        next_cycle <= T2;
-                    elsif exec_cycle = T2 then
-                        d_print("jsr 3");
-                        pcl_a_oe_n <= '1';
-                        pch_a_oe_n <= '1';
-                        pcl_inc_n <= '1';
-                        dbuf_int_oe_n <= '1';
-                        dl_al_we_n <= '1';
-
-                       --push return addr high into stack.
-                        sp_push_n <= '0';
-                        pch_d_oe_n <= '0';
-                        sp_int_a_oe_n <= '0';
-                        r_nw <= '0';
-                        next_cycle <= T3;
-                    elsif exec_cycle = T3 then
-                        d_print("jsr 4");
-                        pch_d_oe_n <= '1';
-
-                       --push return addr low into stack.
-                        sp_push_n <= '0';
-                        pcl_d_oe_n <= '0';
-                        sp_int_a_oe_n <= '0';
-                        r_nw <= '0';
-
-                        next_cycle <= T4;
-                    elsif exec_cycle = T4 then
-                        d_print("jsr 5");
-                        sp_push_n <= '1';
-                        pcl_d_oe_n <= '1';
-                        sp_int_a_oe_n <= '1';
-                        r_nw <= '1';
-
-                        --fetch last op.
-                        pcl_a_oe_n <= '0';
-                        pch_a_oe_n <= '0';
-                        dbuf_int_oe_n <= '0';
-                        dl_ah_we_n <= '0';
-
-                        next_cycle <= T5;
-                    elsif exec_cycle = T5 then
-                        d_print("jsr 6");
-
-                        pcl_a_oe_n <= '1';
-                        pch_a_oe_n <= '1';
-                        dbuf_int_oe_n <= '1';
-                        dl_ah_we_n <= '1';
-
-                        --load/output  pch
-                        ad_oe_n <= '1';
-                        dl_ah_oe_n <= '0';
-                        pch_a_we_n <= '0';
-
-                        --load pcl.
-                        dl_al_oe_n <= '0';
-                        pcl_a_we_n <= '0';
-
-                        next_cycle <= T0;
-                    end if; --if exec_cycle = T1 then
 
                 -- A.5.4 break
                 elsif instruction = conv_std_logic_vector(16#00#, dsize) then
@@ -1249,44 +887,6 @@ end  procedure;
                 ----------------------------------------
                 elsif instruction = conv_std_logic_vector(16#4c#, dsize) then
                     --abs
-                    if exec_cycle = T1 then
-                        d_print("jmp 2");
-                        --fetch next opcode (abs low).
-                        pcl_a_oe_n <= '0';
-                        pch_a_oe_n <= '0';
-                        pcl_inc_n <= '0';
-                        --latch abs low data.
-                        dbuf_int_oe_n <= '0';
-                        dl_al_we_n <= '0';
-                        next_cycle <= T2;
-                    elsif exec_cycle = T2 then
-                        d_print("jmp 3");
-                        dl_al_we_n <= '1';
-
-                        --fetch abs hi
-                        pcl_a_oe_n <= '0';
-                        pch_a_oe_n <= '0';
-                        dbuf_int_oe_n <= '0';
-                        dl_ah_we_n <= '0';
-                        next_cycle <= T3;
-                    elsif exec_cycle = T3 then
-                        d_print("jmp done > next fetch");
-                        pcl_a_oe_n <= '1';
-                        pch_a_oe_n <= '1';
-                        dl_ah_we_n <= '1';
-
-                        --latch > al/ah.
-                        dl_al_oe_n <= '0';
-                        dl_ah_oe_n <= '0';
-
-                        --fetch inst and goto decode next.
-                        dbuf_int_oe_n <= '1';
-                        pcl_a_we_n <= '0';
-                        pch_a_we_n <= '0';
-                        inst_we_n <= '0';
-                        pcl_inc_n <= '0';
-                        next_cycle <= T1;
-                    end if;
 
                 elsif instruction = conv_std_logic_vector(16#6c#, dsize) then
                     --(indir)
@@ -1296,55 +896,6 @@ end  procedure;
                 -- A.5.7 return from soubroutine
                 ----------------------------------------
                 elsif instruction = conv_std_logic_vector(16#60#, dsize) then
-                    if exec_cycle = T1 then
-                        pcl_a_oe_n <= '1';
-                        pch_a_oe_n <= '1';
-                        pcl_inc_n <= '1';
-
-                        --pop stack (decrement only)
-                        sp_pop_n <= '0';
-                        sp_int_a_oe_n <= '0';
-
-                        next_cycle <= T2;
-                    elsif exec_cycle = T2 then
-                        d_print("rts 3");
-                        --pop pcl
-                        sp_int_a_oe_n <= '0';
-                        sp_pop_n <= '0';
-                        --load lo addr.
-                        dbuf_int_oe_n <= '0';
-                        pcl_d_we_n <= '0';
-
-                        next_cycle <= T3;
-                    elsif exec_cycle = T3 then
-                        d_print("rts 4");
-                        --stack decrement stop.
-                        sp_pop_n <= '1';
-                        pcl_d_we_n <= '1';
-
-                        --pop pch
-                        sp_int_a_oe_n <= '0';
-                        --load hi addr.
-                        dbuf_int_oe_n <= '0';
-                        pch_d_we_n <= '0';
-
-                        next_cycle <= T4;
-                    elsif exec_cycle = T4 then
-                        d_print("rts 5");
-                        sp_int_a_oe_n <= '1';
-                        pch_d_we_n <= '1';
-                        dbuf_int_oe_n <= '1';
-
-                        --empty cycle.
-                        --complying h/w manual...
-                        next_cycle <= T5;
-                    elsif exec_cycle = T5 then
-                        d_print("rts 6");
-
-                        --increment pc.
-                        pcl_inc_n <= '0';
-                        next_cycle <= T0;
-                    end if; --if exec_cycle = T1 then
 
                 ----------------------------------------
                 -- A.5.8 branch operations
@@ -1374,10 +925,6 @@ end  procedure;
 
                 else
                     ---unknown instruction!!!!
-                    pcl_inc_n <= '1';
-                    pcl_a_oe_n <= '0';
-                    pch_a_oe_n <= '0';
-                    inst_we_n <= '1';
                     assert false 
                         report "======== unknow instruction " 
                             & conv_hex8(conv_integer(instruction));
@@ -1386,58 +933,19 @@ end  procedure;
             elsif exec_cycle = R0 then
                 d_print(string'("reset"));
 
-                alu_en_n <= '1';
-                ad_oe_n <= '1';
-                pcl_d_we_n <= '1';
-                pcl_a_we_n <= '1';
-                pcl_d_oe_n <= '1';
-                pcl_a_oe_n <= '1';
-                pcl_rel_we_n <= '1';
-                pcl_rel_calc_n <= '1';
-                pch_d_we_n <= '1';
-                pch_a_we_n <= '1';
-                pch_d_oe_n <= '1';
-                pch_a_oe_n <= '1';
-                pcl_inc_n <= '1';
-                inst_we_n <= '1';
-                dbuf_int_oe_n <= '1';
-                dl_al_we_n <= '1';
-                dl_ah_we_n <= '1';
-                dl_al_oe_n <= '1';
-                dl_ah_oe_n <= '1';
-                sp_we_n <= '1';
-                sp_push_n <= '1';
-                sp_pop_n <= '1';
-                sp_int_d_oe_n <= '1';
-                sp_int_a_oe_n <= '1';
-                acc_d_we_n <= '1';
-                acc_alu_we_n <= '1';
-                acc_d_oe_n <= '1';
-                x_we_n <= '1';
-                x_oe_n <= '1';
-                y_we_n <= '1';
-                y_oe_n <= '1';
-                x_inc_n <= '1';
-                x_dec_n <= '1';
-                y_inc_n <= '1';
-                y_dec_n <= '1';
-
-                stat_dec_oe_n <= '1';
-                stat_bus_oe_n <= '1';
-                stat_set_flg_n <= '1';
-                stat_flg <= '1';
-                stat_bus_all_n <= '1';
-                stat_bus_nz_n <= '1';
-                stat_alu_we_n <= '1';
-                x_ea_oe_n <= '1';
-                y_ea_oe_n <= '1';
-                ea_calc_n <= '1';
-                ea_zp_n <= '1';
-                ea_pg_next_n <= '1';
+                pcl_cmd <= "1111";
+                pch_cmd <= "1111";
+                sp_cmd <= "1111";
+                acc_cmd <= "1111";
+                x_cmd <= "1111";
+                y_cmd <= "1111";
+                r_nw <= '1';
 
                 next_cycle <= R1;
             elsif exec_cycle = R1 then
                 next_cycle <= R2;
+                front_we(pch_cmd, '1');
+                back_we(pcl_cmd, '1');
 
             elsif exec_cycle = R2 then
                 next_cycle <= R3;
diff --git a/simulation/cpu/mos6502.vhd b/simulation/cpu/mos6502.vhd
index 2864ecb..1730304 100644
--- a/simulation/cpu/mos6502.vhd
+++ b/simulation/cpu/mos6502.vhd
@@ -21,259 +21,103 @@ end mos6502;
 
 architecture rtl of mos6502 is
 
-    component pc
-        generic (
-                dsize : integer := 8;
-                reset_addr : integer := 0
-                );
-        port (  
-                clk             : in std_logic;
-                res_n           : in std_logic;
-                pc_type         : in std_logic;
-                dbus_we_n       : in std_logic;
-                abus_we_n       : in std_logic;
-                dbus_oe_n       : in std_logic;
-                abus_oe_n       : in std_logic;
-                addr_inc_n      : in std_logic;
-                addr_dec_n      : in std_logic;
-                add_carry       : out std_logic;
-                rel_we_n        : in std_logic;
-                rel_calc_n      : in std_logic;
-                rel_prev        : out std_logic;
-                int_d_bus       : inout std_logic_vector (dsize - 1 downto 0);
-                int_a_bus       : inout std_logic_vector (dsize - 1 downto 0)
-            );
-    end component;
-
-    component decoder
-        generic (dsize : integer := 8);
-        port (  set_clk         : in std_logic;
-                trig_clk        : in std_logic;
-                res_n           : in std_logic;
-                irq_n           : in std_logic;
-                nmi_n           : in std_logic;
-                rdy             : in std_logic;
-                instruction     : in std_logic_vector (dsize - 1 downto 0);
-                exec_cycle      : in std_logic_vector (4 downto 0);
-                next_cycle      : out std_logic_vector (4 downto 0);
-                status_reg      : inout std_logic_vector (dsize - 1 downto 0);
-                inst_we_n       : out std_logic;
-                alu_en_n        : out std_logic;
-                ad_oe_n         : out std_logic;
-                pcl_inc_n       : out std_logic;
-                pcl_d_we_n      : out std_logic;
-                pcl_a_we_n      : out std_logic;
-                pcl_d_oe_n      : out std_logic;
-                pcl_a_oe_n      : out std_logic;
-                pcl_rel_we_n    : out std_logic;
-                pcl_rel_calc_n  : out std_logic;
-                pch_d_we_n      : out std_logic;
-                pch_a_we_n      : out std_logic;
-                pch_d_oe_n      : out std_logic;
-                pch_a_oe_n      : out std_logic;
-                rel_pg_crs_n    : in std_logic;
-                dbuf_int_oe_n   : out std_logic;
-                dl_al_we_n      : out std_logic;
-                dl_ah_we_n      : out std_logic;
-                dl_al_oe_n      : out std_logic;
-                dl_ah_oe_n      : out std_logic;
-                sp_we_n         : out std_logic;
-                sp_push_n       : out std_logic;
-                sp_pop_n        : out std_logic;
-                sp_int_d_oe_n   : out std_logic;
-                sp_int_a_oe_n   : out std_logic;
-                acc_d_we_n      : out std_logic;
-                acc_alu_we_n    : out std_logic;
-                acc_d_oe_n      : out std_logic;
-                x_we_n          : out std_logic;
-                x_oe_n          : out std_logic;
-                x_ea_oe_n       : out std_logic;
-                x_inc_n         : out std_logic;
-                x_dec_n         : out std_logic;
-                y_we_n          : out std_logic;
-                y_oe_n          : out std_logic;
-                y_ea_oe_n       : out std_logic;
-                y_inc_n         : out std_logic;
-                y_dec_n         : out std_logic;
-                ea_calc_n       : out std_logic;
-                ea_zp_n         : out std_logic;
-                ea_pg_next_n    : out std_logic;
-                ea_carry        : in  std_logic;
-                stat_dec_oe_n   : out std_logic;
-                stat_bus_oe_n   : out std_logic;
-                stat_set_flg_n  : out std_logic;
-                stat_flg        : out std_logic;
-                stat_bus_all_n  : out std_logic;
-                stat_bus_nz_n   : out std_logic;
-                stat_alu_we_n   : out std_logic;
-                r_nw            : out std_logic
-                ;---for parameter check purpose!!!
-                check_bit     : out std_logic_vector(1 to 5)
-            );
-    end component;
-
-
-    component alu
-        generic (   dsize : integer := 8
-                );
-        port (  clk             : in std_logic;
-                alu_en_n        : in std_logic;
-                instruction     : in std_logic_vector (dsize - 1 downto 0);
-                int_d_bus       : inout std_logic_vector (dsize - 1 downto 0);
-                acc_out         : in std_logic_vector (dsize - 1 downto 0);
-                acc_in          : out std_logic_vector (dsize - 1 downto 0);
-                carry_in        : in std_logic;
-                negative        : out std_logic;
-                zero            : out std_logic;
-                carry_out       : out std_logic;
-                overflow        : out std_logic
+    ----------------------------------------------
+    ------------ decoder declaration -------------
+    ----------------------------------------------
+component decoder
+    generic (dsize : integer := 8);
+    port (  set_clk         : in std_logic;
+            trig_clk        : in std_logic;
+            res_n           : in std_logic;
+            irq_n           : in std_logic;
+            nmi_n           : in std_logic;
+            rdy             : in std_logic;
+            instruction     : in std_logic_vector (dsize - 1 downto 0);
+            exec_cycle      : in std_logic_vector (5 downto 0);
+            next_cycle      : out std_logic_vector (5 downto 0);
+            status_reg      : inout std_logic_vector (dsize - 1 downto 0);
+            inst_we_n       : out std_logic;
+            ad_oe_n         : out std_logic;
+            pcl_cmd         : out std_logic_vector(3 downto 0);
+            pch_cmd         : out std_logic_vector(3 downto 0);
+            sp_cmd          : out std_logic_vector(3 downto 0);
+            acc_cmd         : out std_logic_vector(3 downto 0);
+            x_cmd           : out std_logic_vector(3 downto 0);
+            y_cmd           : out std_logic_vector(3 downto 0);
+            r_nw            : out std_logic
+            ;---for parameter check purpose!!!
+            check_bit     : out std_logic_vector(1 to 5)
         );
-    end component;
+end component;
 
     ----------------------------------------------
-    ---------- register declareration ------------
+    ------------ register declaration ------------
     ----------------------------------------------
-    component dff
-        generic (
-                dsize : integer := 8
-                );
-        port (  
-                clk     : in std_logic;
-                we_n    : in std_logic;
-                oe_n    : in std_logic;
-                d       : in std_logic_vector (dsize - 1 downto 0);
-                q       : out std_logic_vector (dsize - 1 downto 0)
-            );
-    end component;
-
-    component dbus_buf
-        generic (
-                dsize : integer := 8
-                );
-        port (  
-                clk         : in std_logic;
-                r_nw        : in std_logic;
-                int_oe_n    : in std_logic;
-                int_dbus : inout std_logic_vector (dsize - 1 downto 0);
-                ext_dbus : inout std_logic_vector (dsize - 1 downto 0)
-            );
-    end component;
-
-    component input_dl
-        generic (
-                dsize : integer := 8
-                );
-        port (  
-                clk         : in std_logic;
-                al_we_n     : in std_logic;
-                ah_we_n     : in std_logic;
-                al_oe_n     : in std_logic;
-                ah_oe_n     : in std_logic;
-                int_dbus    : in std_logic_vector (dsize - 1 downto 0);
-                ea_al       : out std_logic_vector (dsize - 1 downto 0);
-                ea_ah       : out std_logic_vector (dsize - 1 downto 0)
-            );
-    end component;
-
-    component sp
-        generic (
-                dsize : integer := 8
-                );
-        port (  
-                clk         : in std_logic;
-                we_n        : in std_logic;
-                push_n      : in std_logic;
-                pop_n       : in std_logic;
-                int_d_oe_n  : in std_logic;
-                int_a_oe_n  : in std_logic;
-                int_dbus    : inout std_logic_vector (dsize - 1 downto 0);
-                int_abus_l  : out std_logic_vector (dsize - 1 downto 0);
-                int_abus_h  : out std_logic_vector (dsize - 1 downto 0)
-            );
-    end component;
-
-    component tsb
-        generic (
-                dsize : integer := 8
-                );
-        port (  
-                oe_n    : in std_logic;
-                d       : in std_logic_vector (dsize - 1 downto 0);
-                q       : out std_logic_vector (dsize - 1 downto 0)
+component d_flip_flop
+    generic (
+            dsize : integer := 8
             );
-    end component;
+    port (  
+            clk     : in std_logic;
+            res_n   : in std_logic;
+            set_n   : in std_logic;
+            we_n    : in std_logic;
+            d       : in std_logic_vector (dsize - 1 downto 0);
+            q       : out std_logic_vector (dsize - 1 downto 0)
+        );
+end component;
 
-    component processor_status 
+component dual_dff
     generic (
             dsize : integer := 8
             );
     port (  
-            clk         : in std_logic;
-            res_n       : in std_logic;
-            dec_oe_n    : in std_logic;
-            bus_oe_n    : in std_logic;
-            set_flg_n   : in std_logic;
-            flg_val     : in std_logic;
-            load_bus_all_n : in std_logic;
-            load_bus_nz_n  : in std_logic;
-            alu_we_n    : in std_logic;
-            alu_n       : in std_logic;
-            alu_v       : in std_logic;
-            alu_z       : in std_logic;
-            alu_c       : in std_logic;
-            decoder     : inout std_logic_vector (dsize - 1 downto 0);
-            int_dbus    : inout std_logic_vector (dsize - 1 downto 0)
+            clk             : in std_logic;
+            res_n           : in std_logic;
+            set_n           : in std_logic;
+            gate_cmd        : in std_logic_vector (3 downto 0);
+            front_port      : inout std_logic_vector (dsize - 1 downto 0);
+            back_in_port    : in std_logic_vector (dsize - 1 downto 0);
+            back_out_port   : out std_logic_vector (dsize - 1 downto 0)
         );
-    end component;
+end component;
 
-    component accumulator
+component data_bus_buffer
     generic (
             dsize : integer := 8
             );
     port (  
             clk         : in std_logic;
-            d_we_n      : in std_logic;
-            alu_we_n    : in std_logic;
-            d_oe_n      : in std_logic;
-            int_dbus    : inout std_logic_vector (dsize - 1 downto 0);
-            alu_out     : in std_logic_vector (dsize - 1 downto 0);
-            alu_in      : out std_logic_vector (dsize - 1 downto 0)
+            r_nw        : in std_logic;
+            int_oe_n    : in std_logic;
+            int_dbus : inout std_logic_vector (dsize - 1 downto 0);
+            ext_dbus : inout std_logic_vector (dsize - 1 downto 0)
         );
-    end component;
+end component;
 
-    component index_reg
+component input_data_latch
     generic (
             dsize : integer := 8
             );
     port (  
             clk         : in std_logic;
-            d_we_n      : in std_logic;
-            d_oe_n      : in std_logic;
-            ea_oe_n     : in std_logic;
-            inc_n       : in std_logic;
-            dec_n       : in std_logic;
-            int_dbus    : inout std_logic_vector (dsize - 1 downto 0);
-            ea_bus      : out std_logic_vector (dsize - 1 downto 0);
-            n           : out std_logic;
-            z           : out std_logic
+            oe_n        : in std_logic;
+            we_n        : in std_logic;
+            int_dbus    : in std_logic_vector (dsize - 1 downto 0);
+            alu_bus     : out std_logic_vector (dsize - 1 downto 0)
         );
-    end component;
+end component;
 
-    component effective_adder
-    generic (   dsize : integer := 8
+component tri_state_buffer
+    generic (
+            dsize : integer := 8
             );
     port (  
-            ea_calc_n       : in std_logic;
-            zp_n            : in std_logic;
-            pg_next_n       : in std_logic;
-            base_l          : in std_logic_vector (dsize - 1 downto 0);
-            base_h          : in std_logic_vector (dsize - 1 downto 0);
-            index           : in std_logic_vector (dsize - 1 downto 0);
-            ah_bus          : out std_logic_vector (dsize - 1 downto 0);
-            al_bus          : out std_logic_vector (dsize - 1 downto 0);
-            carry           : out std_logic
-    );
-    end component;
+            oe_n    : in std_logic;
+            d       : in std_logic_vector (dsize - 1 downto 0);
+            q       : out std_logic_vector (dsize - 1 downto 0)
+        );
+end component;
 
     ----------------------------------------------
     ------------ signal declareration ------------
@@ -281,97 +125,71 @@ architecture rtl of mos6502 is
     signal set_clk : std_logic;
     signal trigger_clk : std_logic;
 
-    signal pcl_inc_n : std_logic;
-    signal pcl_d_we_n : std_logic;
-    signal pcl_a_we_n : std_logic;
-    signal pcl_d_oe_n : std_logic;
-    signal pcl_a_oe_n : std_logic;
-    signal pcl_rel_we_n : std_logic;
-    signal pcl_rel_calc_n : std_logic;
-    signal pch_d_we_n : std_logic;
-    signal pch_a_we_n : std_logic;
-    signal pch_d_oe_n : std_logic;
-    signal pch_a_oe_n : std_logic;
-    signal pc_cry : std_logic;
-    signal pc_cry_n : std_logic;
-    signal dum_terminate : std_logic := 'Z';
-    signal pc_rel_prev : std_logic;
-    signal pc_rel_prev_n : std_logic;
-    signal rel_pg_crs_n : std_logic;
+    signal exec_cycle : std_logic_vector(5 downto 0);
+    signal next_cycle : std_logic_vector(5 downto 0);
+    signal status_reg : std_logic_vector (dsize - 1 downto 0);
 
+    -------------------------------
+    -------- control lines --------
+    -------------------------------
     signal inst_we_n : std_logic;
+    signal ad_oe_n : std_logic;
+
     signal dbuf_r_nw : std_logic;
     signal dbuf_int_oe_n : std_logic;
+
     signal dl_al_we_n : std_logic;
     signal dl_ah_we_n : std_logic;
     signal dl_al_oe_n : std_logic;
     signal dl_ah_oe_n : std_logic;
 
-    signal sp_we_n : std_logic;
-    signal sp_push_n : std_logic;
-    signal sp_pop_n : std_logic;
-    signal sp_int_d_oe_n : std_logic;
-    signal sp_int_a_oe_n : std_logic;
-
-    signal acc_d_we_n      : std_logic;
-    signal acc_alu_we_n    : std_logic;
-    signal acc_d_oe_n      : std_logic;
-    signal alu_en_n        : std_logic;
-    signal alu_in          : std_logic_vector(dsize - 1 downto 0);
-    signal alu_out         : std_logic_vector(dsize - 1 downto 0);
-
-    signal x_we_n : std_logic;
-    signal x_oe_n : std_logic;
-    signal x_inc_n : std_logic;
-    signal x_dec_n : std_logic;
-
-    signal y_we_n : std_logic;
-    signal y_oe_n : std_logic;
-    signal y_inc_n : std_logic;
-    signal y_dec_n : std_logic;
-
-    signal ea_base_l : std_logic_vector(dsize - 1 downto 0);
-    signal ea_base_h : std_logic_vector(dsize - 1 downto 0);
-    signal ea_calc_n : std_logic;
-    signal ea_zp_n : std_logic;
-    signal ea_pg_next_n : std_logic;
-    signal ea_carry : std_logic;
-
-    signal ea_index : std_logic_vector(dsize - 1 downto 0);
-    signal x_ea_oe_n : std_logic;
-    signal y_ea_oe_n : std_logic;
-
-    signal stat_dec_oe_n : std_logic;
-    signal stat_bus_oe_n : std_logic;
-    signal stat_set_flg_n : std_logic;
-    signal stat_flg : std_logic;
-    signal stat_bus_all_n : std_logic;
-    signal stat_bus_nz_n : std_logic;
-    signal stat_alu_we_n : std_logic;
-
-    signal alu_n : std_logic;
-    signal alu_v : std_logic;
-    signal alu_z : std_logic;
-    signal alu_c : std_logic;
-
-    --internal bus (address hi/lo, data)
-    signal ad_oe_n : std_logic;
-    signal internal_abus_h : std_logic_vector (dsize - 1 downto 0);
-    signal internal_abus_l : std_logic_vector (dsize - 1 downto 0);
-    signal internal_dbus : std_logic_vector (dsize - 1 downto 0);
+    ----control line for dual port registers.
+    signal pcl_cmd : std_logic_vector(3 downto 0);
+    signal pch_cmd : std_logic_vector(3 downto 0);
+    signal sp_cmd : std_logic_vector(3 downto 0);
+    signal acc_cmd : std_logic_vector(3 downto 0);
+    signal x_cmd : std_logic_vector(3 downto 0);
+    signal y_cmd : std_logic_vector(3 downto 0);
 
-    signal instruction : std_logic_vector (dsize - 1 downto 0);
-    signal exec_cycle  : std_logic_vector (4 downto 0);
-    signal next_cycle  : std_logic_vector (4 downto 0);
-    signal status_reg : std_logic_vector (dsize - 1 downto 0);
+    -------------------------------
+    ------------ buses ------------
+    -------------------------------
+    signal instruction : std_logic_vector(dsize - 1 downto 0);
+    
+    signal alu_h : std_logic_vector(dsize - 1 downto 0);
+    signal alu_l : std_logic_vector(dsize - 1 downto 0);
+    signal index_bus : std_logic_vector(dsize - 1 downto 0);
+
+    signal acc_in : std_logic_vector(dsize - 1 downto 0);
+    signal acc_out : std_logic_vector(dsize - 1 downto 0);
+
+    --not used bus.
+    signal null_bus : std_logic_vector(dsize - 1 downto 0);
+
+    --address bus
+    signal abh : std_logic_vector(dsize - 1 downto 0);
+    signal abl : std_logic_vector(dsize - 1 downto 0);
+
+    ---internal data bus
+    signal d_bus : std_logic_vector(dsize - 1 downto 0);
 
     signal check_bit     : std_logic_vector(1 to 5);
 
 begin
 
-    ---------------------------------------
-    -------------- instances --------------
-    ---------------------------------------
+
+    -- clock generate.
+    phi1 <= input_clk;
+    phi2 <= not input_clk;
+    set_clk <= input_clk;
+    trigger_clk <= not input_clk;
+    r_nw <= dbuf_r_nw;
+
+
+    --------------------------------------------------
+    ------------------- instances --------------------
+    --------------------------------------------------
+
     dec_inst : decoder generic map (dsize) 
             port map(set_clk, 
                     trigger_clk, 
@@ -384,154 +202,76 @@ begin
                     next_cycle,
                     status_reg, 
                     inst_we_n, 
-                    alu_en_n,
                     ad_oe_n, 
-                    pcl_inc_n, 
-                    pcl_d_we_n, 
-                    pcl_a_we_n, 
-                    pcl_d_oe_n, 
-                    pcl_a_oe_n,
-                    pcl_rel_we_n,
-                    pcl_rel_calc_n,
-                    pch_d_we_n, 
-                    pch_a_we_n, 
-                    pch_d_oe_n, 
-                    pch_a_oe_n,
-                    rel_pg_crs_n,
-                    dbuf_int_oe_n, 
-                    dl_al_we_n, 
-                    dl_ah_we_n, 
-                    dl_al_oe_n, 
-                    dl_ah_oe_n,
-                    sp_we_n, 
-                    sp_push_n, 
-                    sp_pop_n, 
-                    sp_int_d_oe_n, 
-                    sp_int_a_oe_n,
-                    acc_d_we_n,
-                    acc_alu_we_n,
-                    acc_d_oe_n,
-                    x_we_n, 
-                    x_oe_n, 
-                    x_ea_oe_n,
-                    x_inc_n,
-                    x_dec_n,
-                    y_we_n, 
-                    y_oe_n, 
-                    y_ea_oe_n,
-                    y_inc_n,
-                    y_dec_n,
-                    ea_calc_n,
-                    ea_zp_n,
-                    ea_pg_next_n,
-                    ea_carry,
-                    stat_dec_oe_n, 
-                    stat_bus_oe_n, 
-                    stat_set_flg_n, 
-                    stat_flg, 
-                    stat_bus_all_n, 
-                    stat_bus_nz_n, 
-                    stat_alu_we_n, 
+                    pcl_cmd,
+                    pch_cmd,
+                    sp_cmd,
+                    acc_cmd,
+                    x_cmd,
+                    y_cmd,
                     dbuf_r_nw
                     , check_bit --check bit.
                     );
 
-    alu_inst : alu generic map (dsize) 
-            port map (trigger_clk, alu_en_n, instruction, 
-                internal_dbus, alu_in, alu_out,
-                status_reg(0), 
-                alu_n, alu_z, alu_c, alu_v
-            );
-
     --cpu execution cycle number
-    exec_cycle_inst : dff generic map (5) 
-            port map(trigger_clk, '0', '0', next_cycle, exec_cycle);
+    exec_cycle_inst : d_flip_flop generic map (6) 
+            port map(trigger_clk, '1', '1', '0', next_cycle, exec_cycle);
 
     --io data buffer
-    data_bus_buffer : dbus_buf generic map (dsize) 
-            port map(set_clk, dbuf_r_nw, dbuf_int_oe_n, internal_dbus, d_io);
-
-    ---effective addres calcurator.
-    ea_calc: effective_adder generic map (dsize)
-            port map (ea_calc_n, ea_zp_n, ea_pg_next_n,
-                    ea_base_l, ea_base_h, ea_index, 
-                    internal_abus_h, internal_abus_l, ea_carry);
+    dbus_buf : data_bus_buffer generic map (dsize) 
+            port map(set_clk, dbuf_r_nw, dbuf_int_oe_n, d_bus, d_io);
 
     --address operand data buffer.
-    input_data_latch : input_dl generic map (dsize) 
-            port map(set_clk, dl_al_we_n, dl_ah_we_n, dl_al_oe_n, dl_ah_oe_n, 
-                    internal_dbus, ea_base_l, ea_base_h);
-
-    pc_l : pc generic map (dsize, 16#00#) 
-            port map(trigger_clk, rst_n, '0', 
-                    pcl_d_we_n, pcl_a_we_n, pcl_d_oe_n, pcl_a_oe_n, 
-                    pcl_inc_n, '1', pc_cry, 
-                    pcl_rel_we_n, pcl_rel_calc_n, pc_rel_prev,  
-                    internal_dbus, internal_abus_l);
-    pc_h : pc generic map (dsize, 16#80#) 
-            port map(trigger_clk, rst_n, '1', 
-                    pch_d_we_n, pch_a_we_n, pch_d_oe_n, pch_a_oe_n, 
-                    pc_cry_n, pc_rel_prev_n, dum_terminate, 
-                    '1', '1', dum_terminate, 
-                    internal_dbus, internal_abus_h);
-
-    instruction_register : dff generic map (dsize) 
-            port map(trigger_clk, inst_we_n, '0', d_io, instruction);
-
-    stack_pointer : sp generic map (dsize) 
-            port map(trigger_clk, sp_we_n, sp_push_n, sp_pop_n, 
-                    sp_int_d_oe_n, sp_int_a_oe_n, 
-                    internal_dbus, internal_abus_l, internal_abus_h);
-
-    status_register : processor_status generic map (dsize) 
-            port map (trigger_clk, rst_n, 
-                    stat_dec_oe_n, stat_bus_oe_n, 
-                    stat_set_flg_n, stat_flg, stat_bus_all_n, stat_bus_nz_n, 
-                    stat_alu_we_n, alu_n, alu_v, alu_z, alu_c,
-                    status_reg, internal_dbus);
-
-    --x/y output pin is connected to effective address calcurator
-    x_reg : index_reg generic map (dsize) 
-            port map(trigger_clk, x_we_n, x_oe_n, x_ea_oe_n, 
-                    x_inc_n, x_dec_n, internal_dbus, ea_index, 
-                    alu_n, alu_z);
-
-    y_reg : index_reg generic map (dsize) 
-            port map(trigger_clk, y_we_n, y_oe_n, y_ea_oe_n, 
-                    y_inc_n, y_dec_n, internal_dbus, ea_index,
-                    alu_n, alu_z);
-
-    acc_reg : accumulator generic map (dsize) 
-            port map(trigger_clk, 
-                    acc_d_we_n, acc_alu_we_n, acc_d_oe_n, 
-                    internal_dbus, alu_out, alu_in);
-
-    -- clock generate.
-    phi1 <= input_clk;
-    phi2 <= not input_clk;
-    set_clk <= input_clk;
-    trigger_clk <= not input_clk;
-
-    pc_cry_n <= not pc_cry;
-    pc_rel_prev_n <= not pc_rel_prev;
-    r_nw <= dbuf_r_nw;
+    idl_l : input_data_latch generic map (dsize) 
+            port map(set_clk, dl_al_oe_n, dl_al_we_n, alu_l, d_bus);
+    idl_h : input_data_latch generic map (dsize) 
+            port map(set_clk, dl_ah_oe_n, dl_ah_we_n, alu_h, d_bus);
+
+    -------- registers --------
+    ir : d_flip_flop generic map (dsize) 
+            port map(trigger_clk, '1', '1', inst_we_n, d_io, instruction);
+
+    pc_l : dual_dff generic map (dsize) 
+            port map(trigger_clk, '1', rst_n, pcl_cmd, d_bus, abl, alu_l);
+    pc_h : dual_dff generic map (dsize) 
+            port map(trigger_clk, '1', rst_n, pch_cmd, d_bus, abh, alu_h);
+
+    sp : dual_dff generic map (dsize) 
+            port map(trigger_clk, rst_n, '1', sp_cmd, d_bus, abl, alu_l);
+
+    x : dual_dff generic map (dsize) 
+            port map(trigger_clk, rst_n, '1', x_cmd, d_bus, null_bus, index_bus);
+    y : dual_dff generic map (dsize) 
+            port map(trigger_clk, rst_n, '1', y_cmd, d_bus, null_bus, index_bus);
+
+    acc : dual_dff generic map (dsize) 
+            port map(trigger_clk, rst_n, '1', acc_cmd, d_bus, acc_in, acc_out);
+
+    ---temporarily...
+    abl <= alu_l;
+    abh <= alu_h;
+    --adh output is controlled by decoder.
+    adh_buf : tri_state_buffer generic map (dsize)
+            port map (ad_oe_n, abh, addr(asize - 1 downto dsize));
+    adl_buf : tri_state_buffer generic map (dsize)
+            port map (ad_oe_n, abl, addr(dsize - 1 downto 0));
 
-    --branch instruction page crossed?
-    rel_pg_crs_n <= pc_cry nand pc_rel_prev;
+    null_bus <= (others => 'Z');
 
-    --adh output is controlled by decoder.
-    adh_buffer : tsb generic map (dsize)
-            port map (ad_oe_n, internal_abus_h, addr(asize - 1 downto dsize));
-    adl_buffer : tsb generic map (dsize)
-            port map (ad_oe_n, internal_abus_l, addr(dsize - 1 downto 0));
 
     reset_p : process (rst_n)
     begin
-        if (rst_n'event and rst_n = '0') then
-
+        if (rst_n = '0') then
+            --reset vector set to pc.
+            d_bus <= "10000000";
+            abl <= "00000000";
+        else
+            d_bus <= (others => 'Z');
+            abl <= (others => 'Z');
         end if;
     end process;
 
+
 ------------------------------------------------------------
 ------------------------ for debug... ----------------------
 ------------------------------------------------------------
@@ -557,10 +297,10 @@ begin
     return hex_chr(tmp2 + 1) & hex_chr(tmp1 + 1);
 end;
     begin
-        if (set_clk = '0' and exec_cycle = "00000") then
+        if (set_clk = '0' and exec_cycle = "000000") then
             --show pc on the T0 (fetch) cycle.
-            d_print("pc : " & conv_hex8(conv_integer(internal_abus_h)) 
-                    & conv_hex8(conv_integer(internal_abus_l)));
+            d_print("pc : " & conv_hex8(conv_integer(abh)) 
+                    & conv_hex8(conv_integer(abl)));
         end if;
     end process;
 
-- 
2.11.0