From aa8367dd13aa767b6af380d784380ed240dd9c8e Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Thu, 13 Sep 2012 15:08:40 +0000 Subject: [PATCH] radeon/llvm: Add optimization for FP_ROUND --- src/gallium/drivers/radeon/R600ISelLowering.cpp | 26 +++++++++++++++++++++++++ src/gallium/drivers/radeon/R600ISelLowering.h | 1 + 2 files changed, 27 insertions(+) diff --git a/src/gallium/drivers/radeon/R600ISelLowering.cpp b/src/gallium/drivers/radeon/R600ISelLowering.cpp index a9b0c70fd95..e84983df514 100644 --- a/src/gallium/drivers/radeon/R600ISelLowering.cpp +++ b/src/gallium/drivers/radeon/R600ISelLowering.cpp @@ -50,6 +50,9 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) : setOperationAction(ISD::SETCC, MVT::i32, Custom); setOperationAction(ISD::SETCC, MVT::f32, Custom); setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom); + + setTargetDAGCombine(ISD::FP_ROUND); + setSchedulingPreference(Sched::VLIW); } @@ -603,3 +606,26 @@ SDValue R600TargetLowering::LowerFormalArguments( } return Chain; } + +//===----------------------------------------------------------------------===// +// Custom DAG Optimizations +//===----------------------------------------------------------------------===// + +SDValue R600TargetLowering::PerformDAGCombine(SDNode *N, + DAGCombinerInfo &DCI) const +{ + SelectionDAG &DAG = DCI.DAG; + + switch (N->getOpcode()) { + // (f32 fp_round (f64 uint_to_fp a)) -> (f32 uint_to_fp a) + case ISD::FP_ROUND: { + SDValue Arg = N->getOperand(0); + if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) { + return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), N->getValueType(0), + Arg.getOperand(0)); + } + break; + } + } + return SDValue(); +} diff --git a/src/gallium/drivers/radeon/R600ISelLowering.h b/src/gallium/drivers/radeon/R600ISelLowering.h index f2999a30aca..017c6dba7a7 100644 --- a/src/gallium/drivers/radeon/R600ISelLowering.h +++ b/src/gallium/drivers/radeon/R600ISelLowering.h @@ -27,6 +27,7 @@ public: virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock * BB) const; virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; + virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; void ReplaceNodeResults(SDNode * N, SmallVectorImpl &Results, SelectionDAG &DAG) const; -- 2.11.0