From ab63a4c95ee25e2591d0c02549faccd8b134f9e7 Mon Sep 17 00:00:00 2001 From: Colin LeMahieu Date: Tue, 30 Dec 2014 22:00:26 +0000 Subject: [PATCH] [Hexagon] Adding indexed store new-value variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225007 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/HexagonInstrInfo.cpp | 2 +- lib/Target/Hexagon/HexagonInstrInfoV4.td | 143 +++++++++++++++++++++---------- test/MC/Disassembler/Hexagon/nv_st.txt | 51 +++++++++++ 3 files changed, 151 insertions(+), 45 deletions(-) diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp index a741414de89..da35791e3f9 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -1559,7 +1559,7 @@ int HexagonInstrInfo::GetDotNewOp(const MachineInstr* MI) const { return Hexagon::STriw_nv_V4; case Hexagon::STriw_indexed_f: - return Hexagon::STriw_indexed_nv_V4; + return Hexagon::S2_storerinew_io; case Hexagon::STriw_shl_V4: return Hexagon::STriw_shl_nv_V4; diff --git a/lib/Target/Hexagon/HexagonInstrInfoV4.td b/lib/Target/Hexagon/HexagonInstrInfoV4.td index 019e2760790..5ba803789d3 100644 --- a/lib/Target/Hexagon/HexagonInstrInfoV4.td +++ b/lib/Target/Hexagon/HexagonInstrInfoV4.td @@ -1097,62 +1097,117 @@ def : Pat <(store s8ExtPred:$src2, (i32 IntRegs:$src1)), // NV/ST + //===----------------------------------------------------------------------===// -// multiclass for new-value store instructions with base + immediate offset. -// -multiclass ST_Idxd_Pbase_nv { - let isPredicatedNew = isPredNew in - def NAME#_nv_V4 : NVInst_V4<(outs), - (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4), - !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", - ") ")#mnemonic#"($src2+#$src3) = $src4.new", - []>, - Requires<[HasV4T]>; -} +let opNewValue = 2, opExtendable = 1, isExtentSigned = 1, isPredicable = 1 in +class T_store_io_nv MajOp> + : NVInst_V4 <(outs), + (ins IntRegs:$src1, ImmOp:$src2, RC:$src3), + mnemonic#"($src1+#$src2) = $src3.new", + [],"",ST_tc_st_SLOT0> { + bits<5> src1; + bits<13> src2; // Actual address offset + bits<3> src3; + bits<11> offsetBits; // Represents offset encoding -multiclass ST_Idxd_Pred_nv { - let isPredicatedFalse = PredNot in { - defm _c#NAME : ST_Idxd_Pbase_nv; - // Predicate new - defm _cdn#NAME : ST_Idxd_Pbase_nv; + let opExtentBits = !if (!eq(mnemonic, "memb"), 11, + !if (!eq(mnemonic, "memh"), 12, + !if (!eq(mnemonic, "memw"), 13, 0))); + + let opExtentAlign = !if (!eq(mnemonic, "memb"), 0, + !if (!eq(mnemonic, "memh"), 1, + !if (!eq(mnemonic, "memw"), 2, 0))); + + let offsetBits = !if (!eq(mnemonic, "memb"), src2{10-0}, + !if (!eq(mnemonic, "memh"), src2{11-1}, + !if (!eq(mnemonic, "memw"), src2{12-2}, 0))); + + let IClass = 0b1010; + + let Inst{27} = 0b0; + let Inst{26-25} = offsetBits{10-9}; + let Inst{24-21} = 0b1101; + let Inst{20-16} = src1; + let Inst{13} = offsetBits{8}; + let Inst{12-11} = MajOp; + let Inst{10-8} = src3; + let Inst{7-0} = offsetBits{7-0}; } -} -let mayStore = 1, isNVStore = 1, hasSideEffects = 0, isExtendable = 1 in +let opExtendable = 2, opNewValue = 3, isPredicated = 1 in +class T_pstore_io_nv MajOp, bit PredNot, bit isPredNew> + : NVInst_V4 <(outs), + (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC:$src4), + !if(PredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", + ") ")#mnemonic#"($src2+#$src3) = $src4.new", + [],"",V2LDST_tc_st_SLOT0> { + bits<2> src1; + bits<5> src2; + bits<9> src3; + bits<3> src4; + bits<6> offsetBits; // Represents offset encoding + + let isPredicatedNew = isPredNew; + let isPredicatedFalse = PredNot; + let opExtentBits = !if (!eq(mnemonic, "memb"), 6, + !if (!eq(mnemonic, "memh"), 7, + !if (!eq(mnemonic, "memw"), 8, 0))); + + let opExtentAlign = !if (!eq(mnemonic, "memb"), 0, + !if (!eq(mnemonic, "memh"), 1, + !if (!eq(mnemonic, "memw"), 2, 0))); + + let offsetBits = !if (!eq(mnemonic, "memb"), src3{5-0}, + !if (!eq(mnemonic, "memh"), src3{6-1}, + !if (!eq(mnemonic, "memw"), src3{7-2}, 0))); + + let IClass = 0b0100; + + let Inst{27} = 0b0; + let Inst{26} = PredNot; + let Inst{25} = isPredNew; + let Inst{24-21} = 0b0101; + let Inst{20-16} = src2; + let Inst{13} = offsetBits{5}; + let Inst{12-11} = MajOp; + let Inst{10-8} = src4; + let Inst{7-3} = offsetBits{4-0}; + let Inst{2} = 0b0; + let Inst{1-0} = src1; + } + +// multiclass for new-value store instructions with base + immediate offset. +// +let mayStore = 1, isNVStore = 1, isNewValue = 1, hasSideEffects = 0, + isExtendable = 1 in multiclass ST_Idxd_nv ImmBits, - bits<5> PredImmBits> { + Operand ImmOp, Operand predImmOp, bits<2> MajOp> { let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in { - let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits, - isPredicable = 1 in - def NAME#_nv_V4 : NVInst_V4<(outs), - (ins IntRegs:$src1, ImmOp:$src2, RC:$src3), - mnemonic#"($src1+#$src2) = $src3.new", - []>, - Requires<[HasV4T]>; - - let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits, - isPredicated = 1 in { - defm Pt : ST_Idxd_Pred_nv; - defm NotPt : ST_Idxd_Pred_nv; - } + def S2_#NAME#new_io : T_store_io_nv ; + // Predicated + def S2_p#NAME#newt_io :T_pstore_io_nv ; + def S2_p#NAME#newf_io :T_pstore_io_nv ; + // Predicated new + def S4_p#NAME#newtnew_io :T_pstore_io_nv ; + def S4_p#NAME#newfnew_io :T_pstore_io_nv ; } } -let addrMode = BaseImmOffset, validSubTargets = HasV4SubT in { +let addrMode = BaseImmOffset, InputType = "imm", isCodeGenOnly = 0 in { let accessSize = ByteAccess in - defm STrib_indexed: ST_Idxd_nv<"memb", "STrib", IntRegs, s11_0Ext, - u6_0Ext, 11, 6>, AddrModeRel; + defm storerb: ST_Idxd_nv<"memb", "STrib", IntRegs, s11_0Ext, + u6_0Ext, 0b00>, AddrModeRel; - let accessSize = HalfWordAccess in - defm STrih_indexed: ST_Idxd_nv<"memh", "STrih", IntRegs, s11_1Ext, - u6_1Ext, 12, 7>, AddrModeRel; + let accessSize = HalfWordAccess, opExtentAlign = 1 in + defm storerh: ST_Idxd_nv<"memh", "STrih", IntRegs, s11_1Ext, + u6_1Ext, 0b01>, AddrModeRel; - let accessSize = WordAccess in - defm STriw_indexed: ST_Idxd_nv<"memw", "STriw", IntRegs, s11_2Ext, - u6_2Ext, 13, 8>, AddrModeRel; + let accessSize = WordAccess, opExtentAlign = 2 in + defm storeri: ST_Idxd_nv<"memw", "STriw", IntRegs, s11_2Ext, + u6_2Ext, 0b10>, AddrModeRel; } // multiclass for new-value store instructions with base + immediate offset. diff --git a/test/MC/Disassembler/Hexagon/nv_st.txt b/test/MC/Disassembler/Hexagon/nv_st.txt index d53e64d7df2..75724f62c1a 100644 --- a/test/MC/Disassembler/Hexagon/nv_st.txt +++ b/test/MC/Disassembler/Hexagon/nv_st.txt @@ -3,6 +3,9 @@ 0x1f 0x40 0x7f 0x70 0x82 0xf5 0xb1 0x3b # CHECK: r31 = r31 # CHECK-NEXT: memb(r17 + r21<<#3) = r2.new +0x1f 0x40 0x7f 0x70 0x15 0xc2 0xb1 0xa1 +# CHECK: r31 = r31 +# CHECK-NEXT: memb(r17+#21) = r2.new 0x1f 0x40 0x7f 0x70 0xe2 0xf5 0xb1 0x34 # CHECK: r31 = r31 # CHECK-NEXT: if (p3) memb(r17+r21<<#3) = r2.new @@ -17,10 +20,27 @@ # CHECK: p3 = r5 # CHECK-NEXT: r31 = r31 # CHECK-NEXT: if (!p3.new) memb(r17+r21<<#3) = r2.new +0x1f 0x40 0x7f 0x70 0xab 0xc2 0xb1 0x40 +# CHECK: r31 = r31 +# CHECK-NEXT: if (p3) memb(r17+#21) = r2.new +0x1f 0x40 0x7f 0x70 0xab 0xc2 0xb1 0x44 +# CHECK: r31 = r31 +# CHECK-NEXT: if (!p3) memb(r17+#21) = r2.new +0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xab 0xc2 0xb1 0x42 +# CHECK: p3 = r5 +# CHECK-NEXT: r31 = r31 +# CHECK-NEXT: if (p3.new) memb(r17+#21) = r2.new +0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xab 0xc2 0xb1 0x46 +# CHECK: p3 = r5 +# CHECK-NEXT: r31 = r31 +# CHECK-NEXT: if (!p3.new) memb(r17+#21) = r2.new 0x1f 0x40 0x7f 0x70 0x8a 0xf5 0xb1 0x3b # CHECK: r31 = r31 # CHECK-NEXT: memh(r17 + r21<<#3) = r2.new +0x1f 0x40 0x7f 0x70 0x15 0xca 0xb1 0xa1 +# CHECK: r31 = r31 +# CHECK-NEXT: memh(r17+#42) = r2.new 0x1f 0x40 0x7f 0x70 0xea 0xf5 0xb1 0x34 # CHECK: r31 = r31 # CHECK-NEXT: if (p3) memh(r17+r21<<#3) = r2.new @@ -35,10 +55,27 @@ # CHECK: p3 = r5 # CHECK-NEXT: r31 = r31 # CHECK-NEXT: if (!p3.new) memh(r17+r21<<#3) = r2.new +0x1f 0x40 0x7f 0x70 0xab 0xca 0xb1 0x40 +# CHECK: r31 = r31 +# CHECK-NEXT: if (p3) memh(r17+#42) = r2.new +0x1f 0x40 0x7f 0x70 0xab 0xca 0xb1 0x44 +# CHECK: r31 = r31 +# CHECK-NEXT: if (!p3) memh(r17+#42) = r2.new +0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xab 0xca 0xb1 0x42 +# CHECK: p3 = r5 +# CHECK-NEXT: r31 = r31 +# CHECK-NEXT: if (p3.new) memh(r17+#42) = r2.new +0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xab 0xca 0xb1 0x46 +# CHECK: p3 = r5 +# CHECK-NEXT: r31 = r31 +# CHECK-NEXT: if (!p3.new) memh(r17+#42) = r2.new 0x1f 0x40 0x7f 0x70 0x92 0xf5 0xb1 0x3b # CHECK: r31 = r31 # CHECK-NEXT: memw(r17 + r21<<#3) = r2.new +0x1f 0x40 0x7f 0x70 0x15 0xd2 0xb1 0xa1 +# CHECK: r31 = r31 +# CHECK-NEXT: memw(r17+#84) = r2.new 0x1f 0x40 0x7f 0x70 0xf2 0xf5 0xb1 0x34 # CHECK: r31 = r31 # CHECK-NEXT: if (p3) memw(r17+r21<<#3) = r2.new @@ -53,3 +90,17 @@ # CHECK: p3 = r5 # CHECK-NEXT: r31 = r31 # CHECK-NEXT: if (!p3.new) memw(r17+r21<<#3) = r2.new +0x1f 0x40 0x7f 0x70 0xab 0xd2 0xb1 0x40 +# CHECK: r31 = r31 +# CHECK-NEXT: if (p3) memw(r17+#84) = r2.new +0x1f 0x40 0x7f 0x70 0xab 0xd2 0xb1 0x44 +# CHECK: r31 = r31 +# CHECK-NEXT: if (!p3) memw(r17+#84) = r2.new +0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xab 0xd2 0xb1 0x42 +# CHECK: p3 = r5 +# CHECK-NEXT: r31 = r31 +# CHECK-NEXT: if (p3.new) memw(r17+#84) = r2.new +0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xab 0xd2 0xb1 0x46 +# CHECK: p3 = r5 +# CHECK-NEXT: r31 = r31 +# CHECK-NEXT: if (!p3.new) memw(r17+#84) = r2.new -- 2.11.0