From ae0814d7693f10bf0418908b12edd51770647894 Mon Sep 17 00:00:00 2001 From: Tim Renouf Date: Thu, 30 May 2019 18:46:34 +0000 Subject: [PATCH] [AMDGPU] Added target-specific attribute amdgpu-max-memory-clause With LLPC, previous investigation has suggested that si-scheduler interacts badly with SiFormMemoryClauses on an XNACK target in some games. That needs further investigation in the future. In the meantime, this commit adds a target-specific attribute to allow us to disable SIFormMemoryClauses by setting it to 1 on a per-function basis for LLPC to use. Differential Revision: https://reviews.llvm.org/D62572 Change-Id: Ia0ca12ce79093cbbe86caded723ffb13384ede92 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362127 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AMDGPU/SIFormMemoryClauses.cpp | 4 +- test/CodeGen/AMDGPU/disable_form_clauses.ll | 65 +++++++++++++++++++++++++++++ 2 files changed, 68 insertions(+), 1 deletion(-) create mode 100644 test/CodeGen/AMDGPU/disable_form_clauses.ll diff --git a/lib/Target/AMDGPU/SIFormMemoryClauses.cpp b/lib/Target/AMDGPU/SIFormMemoryClauses.cpp index 2cbed99beb2..f3c9ad63a80 100644 --- a/lib/Target/AMDGPU/SIFormMemoryClauses.cpp +++ b/lib/Target/AMDGPU/SIFormMemoryClauses.cpp @@ -319,6 +319,8 @@ bool SIFormMemoryClauses::runOnMachineFunction(MachineFunction &MF) { MaxVGPRs = TRI->getAllocatableSet(MF, &AMDGPU::VGPR_32RegClass).count(); MaxSGPRs = TRI->getAllocatableSet(MF, &AMDGPU::SGPR_32RegClass).count(); + unsigned FuncMaxClause = AMDGPU::getIntegerAttribute( + MF.getFunction(), "amdgpu-max-memory-clause", MaxClause); for (MachineBasicBlock &MBB : MF) { MachineBasicBlock::instr_iterator Next; @@ -339,7 +341,7 @@ bool SIFormMemoryClauses::runOnMachineFunction(MachineFunction &MF) { continue; unsigned Length = 1; - for ( ; Next != E && Length < MaxClause; ++Next) { + for ( ; Next != E && Length < FuncMaxClause; ++Next) { if (!isValidClauseInst(*Next, IsVMEM)) break; diff --git a/test/CodeGen/AMDGPU/disable_form_clauses.ll b/test/CodeGen/AMDGPU/disable_form_clauses.ll new file mode 100644 index 00000000000..dd6f03f9817 --- /dev/null +++ b/test/CodeGen/AMDGPU/disable_form_clauses.ll @@ -0,0 +1,65 @@ +; RUN: llc -march=amdgcn -mcpu=gfx902 -verify-machineinstrs -amdgpu-enable-global-sgpr-addr -stop-after=si-form-memory-clauses < %s | FileCheck -check-prefix=GCN %s + +; GCN-LABEL: {{^}}name:{{[ ]*}}vector_clause +; GCN: BUNDLE +; GCN-NEXT: LOAD_DWORDX2 +; GCN-NEXT: LOAD_DWORDX2 +; GCN-NEXT: {{^ *[}]}} +define amdgpu_kernel void @vector_clause(<4 x i32> addrspace(1)* noalias nocapture readonly %arg, <4 x i32> addrspace(1)* noalias nocapture %arg1) { +bb: + %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() + %tmp2 = zext i32 %tmp to i64 + %tmp3 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp2 + %tmp4 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp3, align 16 + %tmp5 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp2 + %tmp6 = add nuw nsw i64 %tmp2, 1 + %tmp7 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp6 + %tmp8 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp7, align 16 + %tmp9 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp6 + %tmp10 = add nuw nsw i64 %tmp2, 2 + %tmp11 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp10 + %tmp12 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp11, align 16 + %tmp13 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp10 + %tmp14 = add nuw nsw i64 %tmp2, 3 + %tmp15 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp14 + %tmp16 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp15, align 16 + %tmp17 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp14 + store <4 x i32> %tmp4, <4 x i32> addrspace(1)* %tmp5, align 16 + store <4 x i32> %tmp8, <4 x i32> addrspace(1)* %tmp9, align 16 + store <4 x i32> %tmp12, <4 x i32> addrspace(1)* %tmp13, align 16 + store <4 x i32> %tmp16, <4 x i32> addrspace(1)* %tmp17, align 16 + ret void +} + +; GCN-LABEL: {{^}}name:{{[ ]*}}no_vector_clause +; GCN-NOT: BUNDLE +define amdgpu_kernel void @no_vector_clause(<4 x i32> addrspace(1)* noalias nocapture readonly %arg, <4 x i32> addrspace(1)* noalias nocapture %arg1) #0 { +bb: + %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() + %tmp2 = zext i32 %tmp to i64 + %tmp3 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp2 + %tmp4 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp3, align 16 + %tmp5 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp2 + %tmp6 = add nuw nsw i64 %tmp2, 1 + %tmp7 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp6 + %tmp8 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp7, align 16 + %tmp9 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp6 + %tmp10 = add nuw nsw i64 %tmp2, 2 + %tmp11 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp10 + %tmp12 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp11, align 16 + %tmp13 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp10 + %tmp14 = add nuw nsw i64 %tmp2, 3 + %tmp15 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp14 + %tmp16 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp15, align 16 + %tmp17 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp14 + store <4 x i32> %tmp4, <4 x i32> addrspace(1)* %tmp5, align 16 + store <4 x i32> %tmp8, <4 x i32> addrspace(1)* %tmp9, align 16 + store <4 x i32> %tmp12, <4 x i32> addrspace(1)* %tmp13, align 16 + store <4 x i32> %tmp16, <4 x i32> addrspace(1)* %tmp17, align 16 + ret void +} + +declare i32 @llvm.amdgcn.workitem.id.x() + +attributes #0 = { "amdgpu-max-memory-clause"="1" } + -- 2.11.0