From b000abd3b3d2f06e9cc60c19dd4c893cb3531d76 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Wed, 7 Sep 2022 12:10:45 +0300 Subject: [PATCH] drm/i915: Do .crtc_compute_clock() earlier MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Currently we calculate a lot of things (pixel rate, watermarks, cdclk) trusting that the DPLL can generate the exact frequency we ask it. In practice that is not true and there can be certain amount of rounding involved. To allow us to eventually get accurate numbers for all our DPLL clock derived state we need to move the DPLL calculation to hapen much earlier. To that end we hoist it up to the just after the fastset checks. For now we just do the easy code motion, and the actual back feeding of the final DPLL clock into the state will come later. A slight change here is that now .crtc_compute_clock() can get called while the shared_dpll is still assigned. But since .crtc_compute_clock() no longer assignes new shared_dplls this is perfectly fine. TODO: I'd actually like to do this before the fastset check so that if the DPLL state should change we actually do the modeset. Which I think is what the video aficionados want, but it might not be what the fans of fastboot want. Not yet sure how to reconcile those conflicting requirements... v2: s/return/goto/ in error handling Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20220907091057.11572-6-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/display/intel_display.c | 9 +++++---- drivers/gpu/drm/i915/display/intel_dpll.c | 3 --- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 807a20626a79..b07fc5f5b111 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -4820,10 +4820,6 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state, crtc_state->update_wm_post = true; if (mode_changed) { - ret = intel_dpll_crtc_compute_clock(state, crtc); - if (ret) - return ret; - ret = intel_dpll_crtc_get_shared_dpll(state, crtc); if (ret) return ret; @@ -6912,6 +6908,11 @@ static int intel_atomic_check(struct drm_device *dev, new_crtc_state, i) { if (intel_crtc_needs_modeset(new_crtc_state)) { any_ms = true; + + ret = intel_dpll_crtc_compute_clock(state, crtc); + if (ret) + goto fail; + continue; } diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c index 81655fdf2c89..6b8d90d72e00 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.c +++ b/drivers/gpu/drm/i915/display/intel_dpll.c @@ -1411,9 +1411,6 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state, drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state)); - if (drm_WARN_ON(&i915->drm, crtc_state->shared_dpll)) - return 0; - memset(&crtc_state->dpll_hw_state, 0, sizeof(crtc_state->dpll_hw_state)); -- 2.11.0