From b2941ae6efc3067809c8610d3ba878f8f2181c38 Mon Sep 17 00:00:00 2001
From: pbrook <pbrook>
Date: Fri, 25 May 2007 23:13:19 +0000
Subject: [PATCH] 2007-03-25  Paul Brook  <paul@codesourcery.com>

	gas/
	* config/tc-arm.c (T2_SUBS_PC_LR): Define.
	(do_t_add_sub): Correctly encode subs pc, lr, #const.
	(do_t_mov_cmp): Correctly encode movs pc, lr.

	gas/testsulte/
	* gas/arm/thumb32.s: Add tests for subs pc, lr.
	* gas/arm/thumb32.d: Change error-output: to stderr:.
	Update expected output.
---
 gas/config/tc-arm.c             | 28 +++++++++++++++++++++++++++-
 gas/testsuite/ChangeLog         |  6 ++++++
 gas/testsuite/gas/arm/thumb32.d |  6 +++++-
 gas/testsuite/gas/arm/thumb32.s |  5 +++++
 4 files changed, 43 insertions(+), 2 deletions(-)

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 2a9c7abb80..2cb28d4eee 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -555,6 +555,8 @@ struct asm_opcode
 #define OPCODE_MASK	0xfe1fffff
 #define V4_STR_BIT	0x00000020
 
+#define T2_SUBS_PC_LR	0xf3de8f00
+
 #define DATA_OP_SHIFT	21
 
 #define T2_OPCODE_MASK	0xfe1fffff
@@ -8439,7 +8441,21 @@ do_t_add_sub (void)
 	  if (inst.size_req == 4
 	      || (inst.size_req != 2 && !opcode))
 	    {
-	      if (Rs == REG_PC)
+	      if (Rd == REG_PC)
+		{
+		  constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
+			     _("only SUBS PC, LR, #const allowed"));
+		  constraint (inst.reloc.exp.X_op != O_constant,
+			      _("expression too complex"));
+		  constraint (inst.reloc.exp.X_add_number < 0
+			      || inst.reloc.exp.X_add_number > 0xff,
+			     _("immediate value out of range"));
+		  inst.instruction = T2_SUBS_PC_LR
+				     | inst.reloc.exp.X_add_number;
+		  inst.reloc.type = BFD_RELOC_UNUSED;
+		  return;
+		}
+	      else if (Rs == REG_PC)
 		{
 		  /* Always use addw/subw.  */
 		  inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
@@ -9486,6 +9502,16 @@ do_t_mov_cmp (void)
 	  || inst.operands[1].shifted)
 	narrow = FALSE;
 
+      /* MOVS PC, LR is encoded as SUBS PC, LR, #0.  */
+      if (opcode == T_MNEM_movs && inst.operands[1].isreg
+	  && !inst.operands[1].shifted
+	  && inst.operands[0].reg == REG_PC
+	  && inst.operands[1].reg == REG_LR)
+	{
+	  inst.instruction = T2_SUBS_PC_LR;
+	  return;
+	}
+
       if (!inst.operands[1].isreg)
 	{
 	  /* Immediate operand.  */
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 8e60e10a2e..e5404a0f24 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2007-03-25  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/thumb32.s: Add tests for subs pc, lr.
+	* gas/arm/thumb32.d: Change error-output: to stderr:.
+	Update expected output.
+
 2007-05-22  Paul Brook  <paul@codesourcery.com>
 
 	* gas/arm/backslash-at.d: Update expected output.
diff --git a/gas/testsuite/gas/arm/thumb32.d b/gas/testsuite/gas/arm/thumb32.d
index 1b602043df..ea68ec64a4 100644
--- a/gas/testsuite/gas/arm/thumb32.d
+++ b/gas/testsuite/gas/arm/thumb32.d
@@ -3,7 +3,7 @@
 # objdump: -dr --prefix-addresses --show-raw-insn
 # The arm-aout and arm-pe ports do not support Thumb branch relocations.
 # not-target: *-*-*aout* *-*-pe
-# error-output: thumb32.l
+# stderr: thumb32.l
 
 .*: +file format .*arm.*
 
@@ -959,3 +959,7 @@ Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> e80d c010 	srsdb	sp, #16
 0[0-9a-f]+ <[^>]+> e9ad c015 	srsia	sp!, #21
 0[0-9a-f]+ <[^>]+> e9ad c00a 	srsia	sp!, #10
+0[0-9a-f]+ <[^>]+> f3de 8f00 	subs	pc, lr, #0
+0[0-9a-f]+ <[^>]+> f3de 8f00 	subs	pc, lr, #0
+0[0-9a-f]+ <[^>]+> f3de 8f04 	subs	pc, lr, #4
+0[0-9a-f]+ <[^>]+> f3de 8fff 	subs	pc, lr, #255
diff --git a/gas/testsuite/gas/arm/thumb32.s b/gas/testsuite/gas/arm/thumb32.s
index 2cc03b548d..7079ea68d5 100644
--- a/gas/testsuite/gas/arm/thumb32.s
+++ b/gas/testsuite/gas/arm/thumb32.s
@@ -775,3 +775,8 @@ srs:
 	srsdb sp, #16
 	srsia sp!, #21
 	srsia sp!, #10
+
+	movs pc, lr
+	subs pc, lr, #0
+	subs pc, lr, #4
+	subs pc, lr, #255
-- 
2.11.0