From b50702274761e0603f4785cdbab6d4f3d817aeb7 Mon Sep 17 00:00:00 2001
From: Sameer AbuAsal <sabuasal@codeaurora.org>
Date: Thu, 12 Apr 2018 19:22:40 +0000
Subject: [PATCH] [RISCV] Add c.mv rs1, rs2 pattern for addi rs1, rs2, 0

Summary:
GCC compresses the pseudo instruction "mv rd, rs",  which is an alias of
"addi rd, rs, 0", to "c.mv rd, rs".

In LLVM we rely on the canonical MC instruction (MCInst) to do our compression
checks and since there is no rule to compress "addi rd, rs, 0" --> "c.mv
rd, rs" we lose this compression opportunity to gcc.

 In this patch we fix that by adding an addi to c.mv compression pattern, the
 instruction "mv rd, rs" will be compressed to "c.mv rd, rs" just like
 gcc does.

Patch by Zhaoshi Zheng (zzheng) and Sameer (sabuasal).

Reviewers: asb, apazos, zzheng, mgrang, shiva0217

Reviewed By: asb

Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, niosHD, kito-cheng, llvm-commits

Differential Revision: https://reviews.llvm.org/D45583

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329939 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/RISCV/RISCVInstrInfoC.td | 2 ++
 test/MC/RISCV/compress-rv32i.s      | 6 ++++++
 2 files changed, 8 insertions(+)

diff --git a/lib/Target/RISCV/RISCVInstrInfoC.td b/lib/Target/RISCV/RISCVInstrInfoC.td
index c1cbfdcb5cf..5d1c62c0b65 100644
--- a/lib/Target/RISCV/RISCVInstrInfoC.td
+++ b/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -675,6 +675,8 @@ def : CompressPat<(ADD GPRNoX0:$rs1, X0, GPRNoX0:$rs2),
                   (C_MV GPRNoX0:$rs1, GPRNoX0:$rs2)>;
 def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs2, X0),
                   (C_MV GPRNoX0:$rs1, GPRNoX0:$rs2)>;
+def : CompressPat<(ADDI GPRNoX0:$rs1, GPRNoX0:$rs2, 0),
+                  (C_MV GPRNoX0:$rs1, GPRNoX0:$rs2)>;
 def : CompressPat<(EBREAK), (C_EBREAK)>;
 def : CompressPat<(JALR X1, GPRNoX0:$rs1, 0),
                   (C_JALR GPRNoX0:$rs1)>;
diff --git a/test/MC/RISCV/compress-rv32i.s b/test/MC/RISCV/compress-rv32i.s
index e368faf55d7..0436a99e5ba 100644
--- a/test/MC/RISCV/compress-rv32i.s
+++ b/test/MC/RISCV/compress-rv32i.s
@@ -20,6 +20,12 @@
 # RUN: | llvm-objdump  -triple riscv64 -mattr=+c -d -riscv-no-aliases - \
 # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
 
+# CHECK-BYTES: 2e 85
+# CHECK-ALIAS: add a0, zero, a1
+# CHECK-INST: c.mv a0, a1
+# CHECK: # encoding:  [0x2e,0x85]
+addi a0, a1, 0
+
 # CHECK-BYTES: e0 1f
 # CHECK-ALIAS: addi s0, sp, 1020
 # CHECK-INST: c.addi4spn s0, sp, 1020
-- 
2.11.0