From b5612d0a25ac7497e1000c965126a43640afcf5e Mon Sep 17 00:00:00 2001
From: Nikita Popov <nikita.ppv@gmail.com>
Date: Tue, 16 Apr 2019 19:05:49 +0000
Subject: [PATCH] [InstCombine] Prune fshl/fshr with masked operands

If a constant shift amount is used, then only some of the LHS/RHS
operand bits are demanded and we may be able to simplify based on
that. InstCombineSimplifyDemanded already had the necessary support
for that, we just weren't calling it with fshl/fshr as root.

In particular, this allows us to relax some masked funnel shifts
into simple shifts, as shown in the tests.

Patch by Shawn Landden.

Differential Revision: https://reviews.llvm.org/D60660

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358515 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Transforms/InstCombine/InstCombineCalls.cpp |  4 ++++
 test/Transforms/InstCombine/fsh.ll              | 20 ++++++++------------
 2 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/lib/Transforms/InstCombine/InstCombineCalls.cpp b/lib/Transforms/InstCombine/InstCombineCalls.cpp
index d8b188ab8f8..dfdf677a797 100644
--- a/lib/Transforms/InstCombine/InstCombineCalls.cpp
+++ b/lib/Transforms/InstCombine/InstCombineCalls.cpp
@@ -2085,6 +2085,10 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
                                           ConstantExpr::getSub(WidthC, ShAmtC));
     }
 
+    // Left or right might be masked.
+    if (SimplifyDemandedInstructionBits(*II))
+      return &CI;
+
     // The shift amount (operand 2) of a funnel shift is modulo the bitwidth,
     // so only the low bits of the shift amount are demanded if the bitwidth is
     // a power-of-2.
diff --git a/test/Transforms/InstCombine/fsh.ll b/test/Transforms/InstCombine/fsh.ll
index c88beb72ce0..88e9eb72630 100644
--- a/test/Transforms/InstCombine/fsh.ll
+++ b/test/Transforms/InstCombine/fsh.ll
@@ -561,8 +561,7 @@ define i16 @fshr_bswap(i16 %x) {
 
 define i32 @fshl_mask_args_same1(i32 %a) {
 ; CHECK-LABEL: @fshl_mask_args_same1(
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[A:%.*]], -65536
-; CHECK-NEXT:    [[TMP2:%.*]] = call i32 @llvm.fshl.i32(i32 [[TMP1]], i32 [[TMP1]], i32 16)
+; CHECK-NEXT:    [[TMP2:%.*]] = lshr i32 [[A:%.*]], 16
 ; CHECK-NEXT:    ret i32 [[TMP2]]
 ;
   %tmp1 = and i32 %a, 4294901760 ; 0xffff0000
@@ -572,8 +571,8 @@ define i32 @fshl_mask_args_same1(i32 %a) {
 
 define i32 @fshl_mask_args_same2(i32 %a) {
 ; CHECK-LABEL: @fshl_mask_args_same2(
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[A:%.*]], 255
-; CHECK-NEXT:    [[TMP2:%.*]] = call i32 @llvm.fshl.i32(i32 [[TMP1]], i32 [[TMP1]], i32 8)
+; CHECK-NEXT:    [[TMP1:%.*]] = shl i32 [[A:%.*]], 8
+; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], 65280
 ; CHECK-NEXT:    ret i32 [[TMP2]]
 ;
   %tmp1 = and i32 %a, 255
@@ -583,8 +582,7 @@ define i32 @fshl_mask_args_same2(i32 %a) {
 
 define i32 @fshl_mask_args_same3(i32 %a) {
 ; CHECK-LABEL: @fshl_mask_args_same3(
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[A:%.*]], 255
-; CHECK-NEXT:    [[TMP2:%.*]] = call i32 @llvm.fshl.i32(i32 [[TMP1]], i32 [[TMP1]], i32 24)
+; CHECK-NEXT:    [[TMP2:%.*]] = shl i32 [[A:%.*]], 24
 ; CHECK-NEXT:    ret i32 [[TMP2]]
 ;
   %tmp1 = and i32 %a, 255
@@ -594,9 +592,8 @@ define i32 @fshl_mask_args_same3(i32 %a) {
 
 define i32 @fshl_mask_args_different(i32 %a) {
 ; CHECK-LABEL: @fshl_mask_args_different(
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[A:%.*]], -65536
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[A]], -16777216
-; CHECK-NEXT:    [[TMP3:%.*]] = call i32 @llvm.fshl.i32(i32 [[TMP2]], i32 [[TMP1]], i32 17)
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr i32 [[A:%.*]], 15
+; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[TMP1]], 130560
 ; CHECK-NEXT:    ret i32 [[TMP3]]
 ;
   %tmp2 = and i32 %a, 4294901760 ; 0xfffff00f
@@ -607,8 +604,7 @@ define i32 @fshl_mask_args_different(i32 %a) {
 
 define <2 x i31> @fshr_mask_args_same_vector(<2 x i31> %a) {
 ; CHECK-LABEL: @fshr_mask_args_same_vector(
-; CHECK-NEXT:    [[TMP1:%.*]] = and <2 x i31> [[A:%.*]], <i31 1000, i31 1000>
-; CHECK-NEXT:    [[TMP3:%.*]] = call <2 x i31> @llvm.fshl.v2i31(<2 x i31> [[A]], <2 x i31> [[TMP1]], <2 x i31> <i31 10, i31 10>)
+; CHECK-NEXT:    [[TMP3:%.*]] = shl <2 x i31> [[A:%.*]], <i31 10, i31 10>
 ; CHECK-NEXT:    ret <2 x i31> [[TMP3]]
 ;
   %tmp1 = and <2 x i31> %a, <i31 1000, i31 1000>
@@ -620,7 +616,7 @@ define <2 x i31> @fshr_mask_args_same_vector(<2 x i31> %a) {
 define <2 x i32> @fshr_mask_args_same_vector2(<2 x i32> %a, <2 x i32> %b) {
 ; CHECK-LABEL: @fshr_mask_args_same_vector2(
 ; CHECK-NEXT:    [[TMP1:%.*]] = and <2 x i32> [[A:%.*]], <i32 1000000, i32 100000>
-; CHECK-NEXT:    [[TMP3:%.*]] = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> [[TMP1]], <2 x i32> [[TMP1]], <2 x i32> <i32 29, i32 29>)
+; CHECK-NEXT:    [[TMP3:%.*]] = lshr exact <2 x i32> [[TMP1]], <i32 3, i32 3>
 ; CHECK-NEXT:    ret <2 x i32> [[TMP3]]
 ;
   %tmp1 = and <2 x i32> %a, <i32 1000000, i32 100000>
-- 
2.11.0