From b6b40cf4e900276c942e1c1f197206c6d00d5e1f Mon Sep 17 00:00:00 2001
From: Krzysztof Parzyszek <kparzysz@codeaurora.org>
Date: Fri, 19 Aug 2016 14:29:43 +0000
Subject: [PATCH] [Hexagon] Check for empty live interval

Patch by Brendon Cahoon.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279249 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/Hexagon/HexagonExpandCondsets.cpp   |  2 ++
 test/CodeGen/Hexagon/expand-condsets-undef2.ll | 47 ++++++++++++++++++++++++++
 2 files changed, 49 insertions(+)
 create mode 100644 test/CodeGen/Hexagon/expand-condsets-undef2.ll

diff --git a/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/lib/Target/Hexagon/HexagonExpandCondsets.cpp
index 1ffb647d6ad..372eb78e738 100644
--- a/lib/Target/Hexagon/HexagonExpandCondsets.cpp
+++ b/lib/Target/Hexagon/HexagonExpandCondsets.cpp
@@ -1140,6 +1140,8 @@ bool HexagonExpandCondsets::coalesceRegisters(RegisterRef R1, RegisterRef R2) {
 
   LiveInterval &L1 = LIS->getInterval(R1.Reg);
   LiveInterval &L2 = LIS->getInterval(R2.Reg);
+  if (L2.empty())
+    return false;
   bool Overlap = L1.overlaps(L2);
 
   DEBUG(dbgs() << "compatible registers: ("
diff --git a/test/CodeGen/Hexagon/expand-condsets-undef2.ll b/test/CodeGen/Hexagon/expand-condsets-undef2.ll
new file mode 100644
index 00000000000..d62d50d8361
--- /dev/null
+++ b/test/CodeGen/Hexagon/expand-condsets-undef2.ll
@@ -0,0 +1,47 @@
+; RUN: llc -march=hexagon < %s
+; REQUIRES: asserts
+
+; Test that the HexagonExpandCondsets pass does not assert due to
+; attempting to shrink a live interval incorrectly.
+
+
+define void @test() #0 {
+entry:
+  br i1 undef, label %cleanup, label %if.end
+
+if.end:
+  %0 = load i32, i32* undef, align 4
+  %sext = shl i32 %0, 16
+  %conv19 = ashr exact i32 %sext, 16
+  br i1 undef, label %cleanup, label %for.body.lr.ph
+
+for.body.lr.ph:
+  br label %for.body
+
+for.body:
+  %bestScoreL16Q4.0278 = phi i16 [ 32767, %for.body.lr.ph ], [ %.sink, %early_termination ]
+  br i1 false, label %for.body44.lr.ph, label %for.cond90.preheader
+
+for.body44.lr.ph:
+  %conv77 = sext i16 %bestScoreL16Q4.0278 to i32
+  unreachable
+
+for.cond90.preheader:
+  br i1 undef, label %early_termination, label %for.body97
+
+for.body97:
+  br i1 undef, label %for.body97, label %early_termination
+
+early_termination:
+  %.sink = select i1 undef, i16 undef, i16 %bestScoreL16Q4.0278
+  %cmp27 = icmp slt i32 undef, %conv19
+  br i1 %cmp27, label %for.body, label %for.end124
+
+for.end124:
+  unreachable
+
+cleanup:
+  ret void
+}
+
+attributes #0 = { nounwind "target-cpu"="hexagonv60" }
-- 
2.11.0