From b6c6bbc98eb7a65921d0143a21a63a3a8994df9f Mon Sep 17 00:00:00 2001 From: astoria-d Date: Mon, 17 Jun 2013 19:52:17 +0900 Subject: [PATCH] jsr working... --- simulation/cpu/alu.vhd | 8 +++ simulation/cpu/decoder.vhd | 138 ++++++++++++++++++++++++++++++++++++++++++++- simulation/cpu/mos6502.vhd | 35 ++++++++---- 3 files changed, 166 insertions(+), 15 deletions(-) diff --git a/simulation/cpu/alu.vhd b/simulation/cpu/alu.vhd index c9ce3d5..8a6549c 100644 --- a/simulation/cpu/alu.vhd +++ b/simulation/cpu/alu.vhd @@ -124,6 +124,7 @@ entity alu is port ( clk : in std_logic; pcl_inc_n : in std_logic; pch_inc_n : in std_logic; + sph_oe_n : in std_logic; abs_ea_n : in std_logic; zp_ea_n : in std_logic; arith_en_n : in std_logic; @@ -235,6 +236,7 @@ begin pcl <= d_out; pcl_inc_carry <= c; + pch <= bah; abl <= bal; abh <= bah; @@ -247,6 +249,10 @@ begin abl <= bal; abh <= bah; + elsif (sph_oe_n = '0') then + --stack operation... + abl <= bal; + abh <= "00000001"; elsif (arith_en_n = '0') then --instruction is aaabbbcc format. if instruction (1 downto 0) = "01" then @@ -314,6 +320,8 @@ begin abl <= bal; abh <= bah; + pcl <= (others => 'Z'); + pch <= (others => 'Z'); pcl_inc_carry <= '0'; end if; --if (pcl_inc_n = '0') then end process; diff --git a/simulation/cpu/decoder.vhd b/simulation/cpu/decoder.vhd index 59c54a3..8dbfa1c 100644 --- a/simulation/cpu/decoder.vhd +++ b/simulation/cpu/decoder.vhd @@ -18,11 +18,16 @@ entity decoder is inst_we_n : out std_logic; ad_oe_n : out std_logic; dbuf_int_oe_n : out std_logic; + dl_al_we_n : out std_logic; + dl_ah_we_n : out std_logic; + dl_al_oe_n : out std_logic; + dl_ah_oe_n : out std_logic; pcl_inc_n : out std_logic; pch_inc_n : out std_logic; pcl_cmd : out std_logic_vector(3 downto 0); pch_cmd : out std_logic_vector(3 downto 0); sp_cmd : out std_logic_vector(3 downto 0); + sph_oe_n : out std_logic; acc_cmd : out std_logic_vector(3 downto 0); x_cmd : out std_logic_vector(3 downto 0); y_cmd : out std_logic_vector(3 downto 0); @@ -165,8 +170,13 @@ begin --disable the last opration pins. dbuf_int_oe_n <= '1'; + dl_al_we_n <= '1'; + dl_ah_we_n <= '1'; + dl_al_oe_n <= '1'; + dl_ah_oe_n <= '1'; pch_inc_n <= '1'; sp_cmd <= "1111"; + sph_oe_n <= '1'; acc_cmd <= "1111"; x_cmd <= "1111"; y_cmd <= "1111"; @@ -298,8 +308,8 @@ end procedure; if (res_n = '0') then --pc l/h is reset vector. - pcl_cmd <= "1011"; - pch_cmd <= "1011"; + pcl_cmd <= "1110"; + pch_cmd <= "1110"; next_cycle <= R0; elsif (res_n'event and res_n = '1') then pcl_cmd <= "1111"; @@ -322,7 +332,9 @@ end procedure; if exec_cycle = T1 then d_print("decode and execute inst: " & conv_hex8(conv_integer(instruction))); - --disable pin for jmp/abs [xy] page boundary case. + --disable pin for jmp + dl_al_oe_n <= '1'; + dl_ah_oe_n <= '1'; back_we(pcl_cmd, '1'); back_we(pch_cmd, '1'); @@ -940,6 +952,77 @@ end procedure; -- A.5.3 jsr ---------------------------------------- elsif instruction = conv_std_logic_vector(16#20#, dsize) then + if exec_cycle = T1 then + d_print("jsr abs 2"); + --fetch opcode. + back_oe(pcl_cmd, '0'); + back_oe(pch_cmd, '0'); + back_we(pcl_cmd, '0'); + pcl_inc_n <= '0'; + dbuf_int_oe_n <= '0'; + --latch adl + dl_al_we_n <= '0'; + next_cycle <= T2; + elsif exec_cycle = T2 then + d_print("jsr 3"); + back_oe(pcl_cmd, '1'); + back_oe(pch_cmd, '1'); + back_we(pcl_cmd, '1'); + pcl_inc_n <= '1'; + dbuf_int_oe_n <= '1'; + dl_al_we_n <= '1'; + + --push return addr high into stack. +-- sp_push_n <= '0'; + sph_oe_n <= '0'; + front_oe(pch_cmd, '0'); + back_oe(sp_cmd, '0'); + r_nw <= '0'; +-- next_cycle <= T3; +-- elsif exec_cycle = T3 then +-- d_print("jsr 4"); +-- pch_d_oe_n <= '1'; +-- +-- --push return addr low into stack. +-- sp_push_n <= '0'; +-- pcl_d_oe_n <= '0'; +-- sp_int_a_oe_n <= '0'; +-- r_nw <= '0'; +-- +-- next_cycle <= T4; +-- elsif exec_cycle = T4 then +-- d_print("jsr 5"); +-- sp_push_n <= '1'; +-- pcl_d_oe_n <= '1'; +-- sp_int_a_oe_n <= '1'; +-- r_nw <= '1'; +-- +-- --fetch last op. +-- pcl_a_oe_n <= '0'; +-- pch_a_oe_n <= '0'; +-- dbuf_int_oe_n <= '0'; +-- dl_ah_we_n <= '0'; +-- +-- next_cycle <= T5; +-- elsif exec_cycle = T5 then +-- d_print("jsr 6"); +-- +-- pcl_a_oe_n <= '1'; +-- pch_a_oe_n <= '1'; +-- dbuf_int_oe_n <= '1'; +-- dl_ah_we_n <= '1'; +-- +-- --load/output pch +-- ad_oe_n <= '1'; +-- dl_ah_oe_n <= '0'; +-- pch_a_we_n <= '0'; +-- +-- --load pcl. +-- dl_al_oe_n <= '0'; +-- pcl_a_we_n <= '0'; +-- +-- next_cycle <= T0; + end if; --if exec_cycle = T1 then -- A.5.4 break elsif instruction = conv_std_logic_vector(16#00#, dsize) then @@ -954,6 +1037,50 @@ end procedure; ---------------------------------------- elsif instruction = conv_std_logic_vector(16#4c#, dsize) then --abs + if exec_cycle = T1 then + d_print("jmp 2"); + --fetch next opcode (abs low). + back_oe(pcl_cmd, '0'); + back_oe(pch_cmd, '0'); + back_we(pcl_cmd, '0'); + pcl_inc_n <= '0'; + + --latch abs low data. + dbuf_int_oe_n <= '0'; + dl_al_we_n <= '0'; + next_cycle <= T2; + elsif exec_cycle = T2 then + d_print("jmp 3"); + dl_al_we_n <= '1'; + + --fetch abs hi + back_oe(pcl_cmd, '0'); + back_oe(pch_cmd, '0'); + back_we(pcl_cmd, '0'); + pcl_inc_n <= '0'; + + --latch in dlh + dbuf_int_oe_n <= '0'; + dl_ah_we_n <= '0'; + next_cycle <= T3; + elsif exec_cycle = T3 then + d_print("jmp done > next fetch"); + back_oe(pcl_cmd, '1'); + back_oe(pch_cmd, '1'); + dbuf_int_oe_n <= '1'; + dl_ah_we_n <= '1'; + + --latch > al/ah. + dl_al_oe_n <= '0'; + dl_ah_oe_n <= '0'; + + --fetch inst and goto decode next. + back_we(pcl_cmd, '0'); + back_we(pch_cmd, '0'); + inst_we_n <= '0'; + pcl_inc_n <= '0'; + next_cycle <= T1; + end if; elsif instruction = conv_std_logic_vector(16#6c#, dsize) then --(indir) @@ -1004,11 +1131,16 @@ end procedure; inst_we_n <= '1'; ad_oe_n <= '1'; dbuf_int_oe_n <= '1'; + dl_al_we_n <= '1'; + dl_ah_we_n <= '1'; + dl_al_oe_n <= '1'; + dl_ah_oe_n <= '1'; pcl_inc_n <= '1'; pch_inc_n <= '1'; pcl_cmd <= "1111"; pch_cmd <= "1111"; sp_cmd <= "1111"; + sph_oe_n <= '1'; acc_cmd <= "1111"; x_cmd <= "1111"; y_cmd <= "1111"; diff --git a/simulation/cpu/mos6502.vhd b/simulation/cpu/mos6502.vhd index 39b0360..4c70245 100644 --- a/simulation/cpu/mos6502.vhd +++ b/simulation/cpu/mos6502.vhd @@ -39,11 +39,16 @@ component decoder inst_we_n : out std_logic; ad_oe_n : out std_logic; dbuf_int_oe_n : out std_logic; + dl_al_we_n : out std_logic; + dl_ah_we_n : out std_logic; + dl_al_oe_n : out std_logic; + dl_ah_oe_n : out std_logic; pcl_inc_n : out std_logic; pch_inc_n : out std_logic; pcl_cmd : out std_logic_vector(3 downto 0); pch_cmd : out std_logic_vector(3 downto 0); sp_cmd : out std_logic_vector(3 downto 0); + sph_oe_n : out std_logic; acc_cmd : out std_logic_vector(3 downto 0); x_cmd : out std_logic_vector(3 downto 0); y_cmd : out std_logic_vector(3 downto 0); @@ -66,6 +71,7 @@ component alu port ( clk : in std_logic; pcl_inc_n : in std_logic; pch_inc_n : in std_logic; + sph_oe_n : in std_logic; abs_ea_n : in std_logic; zp_ea_n : in std_logic; arith_en_n : in std_logic; @@ -225,6 +231,7 @@ end component; signal acc_cmd : std_logic_vector(3 downto 0); signal x_cmd : std_logic_vector(3 downto 0); signal y_cmd : std_logic_vector(3 downto 0); + signal sph_oe_n : std_logic; ---status register signal stat_dec_oe_n : std_logic; @@ -247,8 +254,6 @@ end component; signal acc_in : std_logic_vector(dsize - 1 downto 0); signal acc_out : std_logic_vector(dsize - 1 downto 0); - signal pcl_in : std_logic_vector(dsize - 1 downto 0); - signal pch_in : std_logic_vector(dsize - 1 downto 0); signal pcl_back : std_logic_vector(dsize - 1 downto 0); signal pch_back : std_logic_vector(dsize - 1 downto 0); @@ -304,11 +309,16 @@ begin inst_we_n, ad_oe_n, dbuf_int_oe_n, + dl_al_we_n, + dl_ah_we_n, + dl_al_oe_n, + dl_ah_oe_n, pcl_inc_n, pch_inc_n, pcl_cmd, pch_cmd, sp_cmd, + sph_oe_n, acc_cmd, x_cmd, y_cmd, @@ -327,6 +337,7 @@ begin port map (trigger_clk, pcl_inc_n, pch_inc_n, + sph_oe_n, abs_ea_n, zp_ea_n, arith_en_n, @@ -364,18 +375,18 @@ begin --address operand data buffer. idl_l : input_data_latch generic map (dsize) - port map(set_clk, dl_al_oe_n, dl_al_we_n, bal, d_bus); + port map(set_clk, dl_al_oe_n, dl_al_we_n, d_bus, bal); idl_h : input_data_latch generic map (dsize) - port map(set_clk, dl_ah_oe_n, dl_ah_we_n, bah, d_bus); + port map(set_clk, dl_ah_oe_n, dl_ah_we_n, d_bus, bah); -------- registers -------- ir : d_flip_flop generic map (dsize) port map(trigger_clk, '1', '1', inst_we_n, d_io, instruction); - pc_l : dual_dff generic map (dsize) - port map(trigger_clk, '1', rst_n, pcl_cmd, pcl_in, pcl_back, bal); - pc_h : dual_dff generic map (dsize) - port map(trigger_clk, '1', rst_n, pch_cmd, pch_in, pch_back, bah); + pcl_inst : dual_dff generic map (dsize) + port map(trigger_clk, '1', rst_n, pcl_cmd, d_bus, pcl_back, bal); + pch_inst : dual_dff generic map (dsize) + port map(trigger_clk, '1', rst_n, pch_cmd, d_bus, pch_back, bah); --status register status_register : processor_status generic map (dsize) @@ -410,11 +421,11 @@ begin begin if (rst_n = '0') then --reset vector set to pc. - pcl_in <= reset_l ; - pch_in <= reset_h ; + pcl_back <= reset_l ; + pch_back <= reset_h ; else - pcl_in <= d_bus; - pch_in <= d_bus; + pcl_back <= (others => 'Z'); + pch_back <= (others => 'Z'); end if; end process; -- 2.11.0