From b7909d81f7658f64bba0faed83e7c2fd6a52fcba Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Wed, 5 Dec 2012 07:15:24 +0400 Subject: [PATCH] target-xtensa: implement MISC SR The Miscellaneous Special Registers Option provides zero to four scratch registers within the processor readable and writable by RSR, WSR, and XSR. These registers are privileged. They may be useful for some application-specific exception and interrupt processing tasks in the kernel. The MISC registers are undefined after reset. See ISA, 4.7.3 for details. Signed-off-by: Max Filippov Signed-off-by: Blue Swirl --- target-xtensa/cpu.h | 1 + target-xtensa/overlay_tool.h | 1 + target-xtensa/translate.c | 4 ++++ 3 files changed, 6 insertions(+) diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index a73d32d898..08fd5bc395 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -153,6 +153,7 @@ enum { ICOUNTLEVEL = 237, EXCVADDR = 238, CCOMPARE = 240, + MISC = 244, }; #define PS_INTLEVEL 0xf diff --git a/target-xtensa/overlay_tool.h b/target-xtensa/overlay_tool.h index 0b47029f8c..dd4f51a7b7 100644 --- a/target-xtensa/overlay_tool.h +++ b/target-xtensa/overlay_tool.h @@ -95,6 +95,7 @@ /* Other, TODO */ \ XCHAL_OPTION(XCHAL_HAVE_WINDOWED, XTENSA_OPTION_WINDOWED_REGISTER) | \ XCHAL_OPTION(XCHAL_HAVE_DEBUG, XTENSA_OPTION_DEBUG) |\ + XCHAL_OPTION(XCHAL_NUM_MISC_REGS > 0, XTENSA_OPTION_MISC_SR) | \ XCHAL_OPTION(XCHAL_HAVE_THREADPTR, XTENSA_OPTION_THREAD_POINTER) | \ XCHAL_OPTION(XCHAL_HAVE_PRID, XTENSA_OPTION_PROCESSOR_ID)) diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 3303e5f693..52edcefb05 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -179,6 +179,10 @@ static const XtensaReg sregnames[256] = { XTENSA_OPTION_TIMER_INTERRUPT), [CCOMPARE + 2] = XTENSA_REG("CCOMPARE2", XTENSA_OPTION_TIMER_INTERRUPT), + [MISC] = XTENSA_REG("MISC0", XTENSA_OPTION_MISC_SR), + [MISC + 1] = XTENSA_REG("MISC1", XTENSA_OPTION_MISC_SR), + [MISC + 2] = XTENSA_REG("MISC2", XTENSA_OPTION_MISC_SR), + [MISC + 3] = XTENSA_REG("MISC3", XTENSA_OPTION_MISC_SR), }; static const XtensaReg uregnames[256] = { -- 2.11.0