From b98c549d135c8f38b2fc1b086cc46f0b243ce862 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Mon, 3 May 2010 22:40:32 +0000 Subject: [PATCH] Check that subregisters don't have independent values in RemoveCopyByCommutingDef(). This fixes PR6941. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102970 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SimpleRegisterCoalescing.cpp | 17 +++++++++-- .../X86/2010-05-03-CoalescerSubRegClobber.ll | 33 ++++++++++++++++++++++ 2 files changed, 47 insertions(+), 3 deletions(-) create mode 100644 test/CodeGen/X86/2010-05-03-CoalescerSubRegClobber.ll diff --git a/lib/CodeGen/SimpleRegisterCoalescing.cpp b/lib/CodeGen/SimpleRegisterCoalescing.cpp index 59cf824ca7d..1f68a6f276f 100644 --- a/lib/CodeGen/SimpleRegisterCoalescing.cpp +++ b/lib/CodeGen/SimpleRegisterCoalescing.cpp @@ -259,6 +259,9 @@ bool SimpleRegisterCoalescing::HasOtherReachingDefs(LiveInterval &IntA, for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) { if (BI->valno == BValNo) continue; + // When BValNo is null, we're looking for a dummy clobber-value for a subreg. + if (!BValNo && !BI->valno->isDefAccurate() && !BI->valno->getCopy()) + continue; if (BI->start <= AI->start && BI->end > AI->start) return true; if (BI->start > AI->start && BI->start < AI->end) @@ -369,6 +372,17 @@ bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA, if (HasOtherReachingDefs(IntA, IntB, AValNo, BValNo)) return false; + bool BHasSubRegs = false; + if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) + BHasSubRegs = *tri_->getSubRegisters(IntB.reg); + + // Abort if the subregisters of IntB.reg have values that are not simply the + // clobbers from the superreg. + if (BHasSubRegs) + for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) + if (HasOtherReachingDefs(IntA, li_->getInterval(*SR), AValNo, 0)) + return false; + // If some of the uses of IntA.reg is already coalesced away, return false. // It's not possible to determine whether it's safe to perform the coalescing. for (MachineRegisterInfo::use_nodbg_iterator UI = @@ -417,9 +431,6 @@ bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA, BExtend[ALR->end] = BLR->end; // Update uses of IntA of the specific Val# with IntB. - bool BHasSubRegs = false; - if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) - BHasSubRegs = *tri_->getSubRegisters(IntB.reg); for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg), UE = mri_->use_end(); UI != UE;) { MachineOperand &UseMO = UI.getOperand(); diff --git a/test/CodeGen/X86/2010-05-03-CoalescerSubRegClobber.ll b/test/CodeGen/X86/2010-05-03-CoalescerSubRegClobber.ll new file mode 100644 index 00000000000..323925c7ff6 --- /dev/null +++ b/test/CodeGen/X86/2010-05-03-CoalescerSubRegClobber.ll @@ -0,0 +1,33 @@ +; RUN: llc < %s | FileCheck %s +; PR6941 +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.0.0" + +define i32 @snd_xbytes(i32 %v, i32 %from, i32 %to) nounwind readnone ssp { +entry: + %cmp19 = icmp eq i32 %to, 0 ; [#uses=1] + br i1 %cmp19, label %while.end, label %while.cond + +while.cond: ; preds = %entry, %while.cond + %y.021 = phi i32 [ %rem, %while.cond ], [ %to, %entry ] ; [#uses=3] + %x.020 = phi i32 [ %y.021, %while.cond ], [ %from, %entry ] ; [#uses=1] + %rem = urem i32 %x.020, %y.021 ; [#uses=2] + %cmp = icmp eq i32 %rem, 0 ; [#uses=1] + br i1 %cmp, label %while.end, label %while.cond + +while.end: ; preds = %while.cond, %entry + %x.0.lcssa = phi i32 [ %from, %entry ], [ %y.021, %while.cond ] ; [#uses=2] + %div = udiv i32 %from, %x.0.lcssa ; [#uses=1] + %div11 = udiv i32 %to, %x.0.lcssa ; [#uses=1] + %conv = zext i32 %v to i64 ; [#uses=1] + %conv14 = zext i32 %div11 to i64 ; [#uses=1] +; Verify that we don't clobber %eax after putting the imulq result in %rax +; CHECK: imulq %r{{.}}x, %r[[RES:.]]x +; CHECK-NOT: movl {{.*}}, %e[[RES]]x +; CHECK: div + %mul = mul i64 %conv14, %conv ; [#uses=1] + %conv16 = zext i32 %div to i64 ; [#uses=1] + %div17 = udiv i64 %mul, %conv16 ; [#uses=1] + %conv18 = trunc i64 %div17 to i32 ; [#uses=1] + ret i32 %conv18 +} -- 2.11.0