From b996216384679e9bce5a62e417198da704c09c19 Mon Sep 17 00:00:00 2001 From: Matt Turner Date: Tue, 27 May 2014 18:47:40 -0700 Subject: [PATCH] i965/fs: Add SHADER_OPCODE_LOAD_PAYLOAD. Will be used to simplify the handling of large virtual GRFs in SSA form. Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_defines.h | 14 ++++++++++++++ src/mesa/drivers/dri/i965/brw_fs.cpp | 10 ++++++++++ src/mesa/drivers/dri/i965/brw_fs.h | 2 ++ src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 4 ++++ src/mesa/drivers/dri/i965/brw_shader.cpp | 3 +++ 5 files changed, 33 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 3afd399ab1d..a962c7b7787 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -798,6 +798,20 @@ enum opcode { SHADER_OPCODE_TG4, SHADER_OPCODE_TG4_OFFSET, + /** + * Combines multiple sources of size 1 into a larger virtual GRF. + * For example, parameters for a send-from-GRF message. Or, updating + * channels of a size 4 VGRF used to store vec4s such as texturing results. + * + * This will be lowered into MOVs from each source to consecutive reg_offsets + * of the destination VGRF. + * + * src[0] may be BAD_FILE. If so, the lowering pass skips emitting the MOV, + * but still reserves the first channel of the destination VGRF. This can be + * used to reserve space for, say, a message header set up by the generators. + */ + SHADER_OPCODE_LOAD_PAYLOAD, + SHADER_OPCODE_SHADER_TIME_ADD, SHADER_OPCODE_UNTYPED_ATOMIC, diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index be461ac20c1..fa00c11cfb4 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -241,6 +241,16 @@ fs_visitor::CMP(fs_reg dst, fs_reg src0, fs_reg src1, uint32_t condition) return inst; } +fs_inst * +fs_visitor::LOAD_PAYLOAD(const fs_reg &dst, fs_reg *src, int sources) +{ + fs_inst *inst = new(mem_ctx) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD, dst, src, + sources); + inst->regs_written = sources; + + return inst; +} + exec_list fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_reg &dst, const fs_reg &surf_index, diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h index f9e0daff175..4ce5fa319e1 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.h +++ b/src/mesa/drivers/dri/i965/brw_fs.h @@ -338,6 +338,8 @@ public: fs_inst *end, const fs_reg ®); + fs_inst *LOAD_PAYLOAD(const fs_reg &dst, fs_reg *src, int sources); + exec_list VARYING_PULL_CONSTANT_LOAD(const fs_reg &dst, const fs_reg &surf_index, const fs_reg &varying_offset, diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp index 5e1174c72ef..e8daf347ed2 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp @@ -1749,6 +1749,10 @@ fs_generator::generate_code(exec_list *instructions) _mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode); } abort(); + + case SHADER_OPCODE_LOAD_PAYLOAD: + assert(!"Should be lowered by lower_load_payload()"); + break; } if (inst->conditional_mod) { diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp index 687356bcd04..103c70b8cd5 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.cpp +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp @@ -454,6 +454,9 @@ brw_instruction_name(enum opcode op) case SHADER_OPCODE_SHADER_TIME_ADD: return "shader_time_add"; + case SHADER_OPCODE_LOAD_PAYLOAD: + return "load_payload"; + case SHADER_OPCODE_GEN4_SCRATCH_READ: return "gen4_scratch_read"; case SHADER_OPCODE_GEN4_SCRATCH_WRITE: -- 2.11.0