From baad40b5860c9d355dc499f62d042b679c2afd27 Mon Sep 17 00:00:00 2001 From: Matthias Braun Date: Thu, 28 Apr 2016 03:07:11 +0000 Subject: [PATCH] TableGen: Produce CoveredBySubRegs summary for register classes This will be used in the upcoming "DetectDeadLanes" pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267850 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/Target/TargetRegisterInfo.h | 3 +++ utils/TableGen/CodeGenRegisters.cpp | 7 +++++-- utils/TableGen/CodeGenRegisters.h | 1 + utils/TableGen/RegisterInfoEmitter.cpp | 4 +++- 4 files changed, 12 insertions(+), 3 deletions(-) diff --git a/include/llvm/Target/TargetRegisterInfo.h b/include/llvm/Target/TargetRegisterInfo.h index 7eb506c2269..77705449a2f 100644 --- a/include/llvm/Target/TargetRegisterInfo.h +++ b/include/llvm/Target/TargetRegisterInfo.h @@ -70,6 +70,9 @@ public: const uint8_t AllocationPriority; /// Whether the class supports two (or more) disjunct subregister indices. const bool HasDisjunctSubRegs; + /// Whether a combination of subregisters can cover every register in the + /// class. See also the CoveredBySubRegs description in Target.td. + const bool CoveredBySubRegs; const sc_iterator SuperClasses; ArrayRef (*OrderFunc)(const MachineFunction&); diff --git a/utils/TableGen/CodeGenRegisters.cpp b/utils/TableGen/CodeGenRegisters.cpp index 114ee18a5f3..626144fbe85 100644 --- a/utils/TableGen/CodeGenRegisters.cpp +++ b/utils/TableGen/CodeGenRegisters.cpp @@ -1829,11 +1829,14 @@ void CodeGenRegBank::computeDerivedInfo() { computeRegUnitLaneMasks(); - // Compute register class HasDisjunctSubRegs flag. + // Compute register class HasDisjunctSubRegs/CoveredBySubRegs flag. for (CodeGenRegisterClass &RC : RegClasses) { RC.HasDisjunctSubRegs = false; - for (const CodeGenRegister *Reg : RC.getMembers()) + RC.CoveredBySubRegs = true; + for (const CodeGenRegister *Reg : RC.getMembers()) { RC.HasDisjunctSubRegs |= Reg->HasDisjunctSubRegs; + RC.CoveredBySubRegs &= Reg->CoveredBySubRegs; + } } // Get the weight of each set. diff --git a/utils/TableGen/CodeGenRegisters.h b/utils/TableGen/CodeGenRegisters.h index 83b5996b45b..b8d47aa4ff8 100644 --- a/utils/TableGen/CodeGenRegisters.h +++ b/utils/TableGen/CodeGenRegisters.h @@ -310,6 +310,7 @@ namespace llvm { unsigned LaneMask; /// True if there are at least 2 subregisters which do not interfere. bool HasDisjunctSubRegs; + bool CoveredBySubRegs; // Return the Record that defined this class, or NULL if the class was // created by TableGen. diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp index 4ec3e7de0f7..3316da6185c 100644 --- a/utils/TableGen/RegisterInfoEmitter.cpp +++ b/utils/TableGen/RegisterInfoEmitter.cpp @@ -1311,7 +1311,9 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, << format("0x%08x,\n ", RC.LaneMask) << (unsigned)RC.AllocationPriority << ",\n " << (RC.HasDisjunctSubRegs?"true":"false") - << ", /* HasDisjunctSubRegs */\n "; + << ", /* HasDisjunctSubRegs */\n " + << (RC.CoveredBySubRegs?"true":"false") + << ", /* CoveredBySubRegs */\n "; if (RC.getSuperClasses().empty()) OS << "NullRegClasses,\n "; else -- 2.11.0