From bac740f8ef84522964c9425d1d9d48d29e8e6fe8 Mon Sep 17 00:00:00 2001
From: Sjoerd Meijer <sjoerd.meijer@arm.com>
Date: Tue, 13 Feb 2018 10:29:03 +0000
Subject: [PATCH] [Thumb] Handle addressing mode AddrMode5FP16

This addressing mode wasn't checked, so we were running in an assert.

Differential Revision: https://reviews.llvm.org/D43179


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324996 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/ARM/Thumb2InstrInfo.cpp    | 14 ++++++++++++++
 test/CodeGen/ARM/fp16-instructions.ll | 24 ++++++++++++++++++++++++
 2 files changed, 38 insertions(+)

diff --git a/lib/Target/ARM/Thumb2InstrInfo.cpp b/lib/Target/ARM/Thumb2InstrInfo.cpp
index c5eb14f3e60..e8259f7edc0 100644
--- a/lib/Target/ARM/Thumb2InstrInfo.cpp
+++ b/lib/Target/ARM/Thumb2InstrInfo.cpp
@@ -600,6 +600,20 @@ bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
         Offset = -Offset;
         isSub = true;
       }
+    } else if (AddrMode == ARMII::AddrMode5FP16) {
+      // VFP address mode.
+      const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
+      int InstrOffs = ARM_AM::getAM5FP16Offset(OffOp.getImm());
+      if (ARM_AM::getAM5FP16Op(OffOp.getImm()) == ARM_AM::sub)
+        InstrOffs *= -1;
+      NumBits = 8;
+      Scale = 2;
+      Offset += InstrOffs * 2;
+      assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
+      if (Offset < 0) {
+        Offset = -Offset;
+        isSub = true;
+      }
     } else if (AddrMode == ARMII::AddrModeT2_i8s4) {
       Offset += MI.getOperand(FrameRegIdx + 1).getImm() * 4;
       NumBits = 10; // 8 bits scaled by 4
diff --git a/test/CodeGen/ARM/fp16-instructions.ll b/test/CodeGen/ARM/fp16-instructions.ll
index e792856b9ab..b2b31672ce7 100644
--- a/test/CodeGen/ARM/fp16-instructions.ll
+++ b/test/CodeGen/ARM/fp16-instructions.ll
@@ -695,3 +695,27 @@ entry:
 
 ; CHECK-HARDFP-FULLFP16:       vsub.f16  s0, s0, s1
 }
+
+; Check for VSTRH with a FCONSTH, this checks that addressing mode
+; AddrMode5FP16 is supported.
+define i32 @ThumbAddrMode5FP16(i32 %A.coerce) {
+entry:
+  %S = alloca half, align 2
+  %tmp.0.extract.trunc = trunc i32 %A.coerce to i16
+  %0 = bitcast i16 %tmp.0.extract.trunc to half
+  %S.0.S.0..sroa_cast = bitcast half* %S to i8*
+  store volatile half 0xH3C00, half* %S, align 2
+  %S.0.S.0. = load volatile half, half* %S, align 2
+  %add = fadd half %S.0.S.0., %0
+  %1 = bitcast half %add to i16
+  %tmp2.0.insert.ext = zext i16 %1 to i32
+  ret i32 %tmp2.0.insert.ext
+
+; CHECK-LABEL:            ThumbAddrMode5FP16
+
+; CHECK-SOFTFP-FULLFP16:  vmov.f16    [[S0:s[0-9]]], #1.000000e+00
+; CHECK-SOFTFP-FULLFP16:  vstr.16     [[S0]], [sp, #{{.}}]
+; CHECK-SOFTFP-FULLFP16:  vmov.f16    [[S0_2:s[0-9]]], r0
+; CHECK-SOFTFP-FULLFP16:  vldr.16     [[S2:s[0-9]]], [sp, #{{.}}]
+; CHECK-SOFTFP-FULLFP16:  vadd.f16    s{{.}}, [[S2]], [[S0_2]]
+}
-- 
2.11.0