From bb4bdf4fe4c931e45d0a37e24ec79accd815c1d8 Mon Sep 17 00:00:00 2001 From: Alkis Evlogimenos Date: Thu, 26 Aug 2004 22:21:04 +0000 Subject: [PATCH] Add getAllocatableSet() function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16059 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/Target/MRegisterInfo.h | 4 ++++ lib/Target/MRegisterInfo.cpp | 22 ++++++++++++++++++---- 2 files changed, 22 insertions(+), 4 deletions(-) diff --git a/include/llvm/Target/MRegisterInfo.h b/include/llvm/Target/MRegisterInfo.h index 8ec2dde297d..572af3f1d28 100644 --- a/include/llvm/Target/MRegisterInfo.h +++ b/include/llvm/Target/MRegisterInfo.h @@ -160,6 +160,10 @@ public: return Reg >= FirstVirtualRegister; } + /// getAllocatableSet - Returns a bitset indexed by register number + /// indicating if a register is allocatable or not. + std::vector getAllocatableSet(MachineFunction &MF) const; + const MRegisterDesc &operator[](unsigned RegNo) const { assert(RegNo < NumRegs && "Attempting to access record for invalid register number!"); diff --git a/lib/Target/MRegisterInfo.cpp b/lib/Target/MRegisterInfo.cpp index 7c1028bc323..30b54a6414d 100644 --- a/lib/Target/MRegisterInfo.cpp +++ b/lib/Target/MRegisterInfo.cpp @@ -28,12 +28,14 @@ MRegisterInfo::MRegisterInfo(const MRegisterDesc *D, unsigned NR, // Fill in the PhysRegClasses map for (MRegisterInfo::regclass_iterator I = regclass_begin(), - E = regclass_end(); I != E; ++I) - for (unsigned i = 0, e = (*I)->getNumRegs(); i != e; ++i) { - unsigned Reg = (*I)->getRegister(i); + E = regclass_end(); I != E; ++I) { + const TargetRegisterClass *RC = *I; + for (unsigned i = 0, e = RC->getNumRegs(); i != e; ++i) { + unsigned Reg = RC->getRegister(i); assert(PhysRegClasses[Reg] == 0 && "Register in more than one class?"); - PhysRegClasses[Reg] = *I; + PhysRegClasses[Reg] = RC; } + } CallFrameSetupOpcode = CFSO; CallFrameDestroyOpcode = CFDO; @@ -44,4 +46,16 @@ MRegisterInfo::~MRegisterInfo() { delete[] PhysRegClasses; } +std::vector MRegisterInfo::getAllocatableSet(MachineFunction &MF) const { + std::vector Allocatable(NumRegs); + for (MRegisterInfo::regclass_iterator I = regclass_begin(), + E = regclass_end(); I != E; ++I) { + const TargetRegisterClass *RC = *I; + for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), + E = RC->allocation_order_end(MF); I != E; ++I) + Allocatable[*I] = true; + } + return Allocatable; +} + } // End llvm namespace -- 2.11.0