From bb85760572ca24a76c3de644ce45cfb69f5a731a Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Sat, 26 Sep 2020 19:05:00 +0200 Subject: [PATCH] drm/ingenic: Add support for 30-bit modes Starting from the JZ4760 SoC, the primary and overlay planes support 30-bit pixel modes (10 bits per color component). Add support for these in the ingenic-drm driver. Signed-off-by: Paul Cercueil Reviewed-by: Sam Ravnborg Link: https://patchwork.freedesktop.org/patch/msgid/20200926170501.1109197-7-paul@crapouillou.net --- drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 8 ++++++++ drivers/gpu/drm/ingenic/ingenic-drm.h | 1 + 2 files changed, 9 insertions(+) diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c index 567facfb7217..b5681379ade5 100644 --- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c +++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c @@ -458,6 +458,9 @@ void ingenic_drm_plane_config(struct device *dev, case DRM_FORMAT_XRGB8888: ctrl |= JZ_LCD_OSDCTRL_BPP_18_24; break; + case DRM_FORMAT_XRGB2101010: + ctrl |= JZ_LCD_OSDCTRL_BPP_30; + break; } regmap_update_bits(priv->map, JZ_REG_LCD_OSDCTRL, @@ -473,6 +476,9 @@ void ingenic_drm_plane_config(struct device *dev, case DRM_FORMAT_XRGB8888: ctrl |= JZ_LCD_CTRL_BPP_18_24; break; + case DRM_FORMAT_XRGB2101010: + ctrl |= JZ_LCD_CTRL_BPP_30; + break; } regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, @@ -1222,12 +1228,14 @@ static const u32 jz4770_formats_f1[] = { DRM_FORMAT_XRGB1555, DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888, + DRM_FORMAT_XRGB2101010, }; static const u32 jz4770_formats_f0[] = { DRM_FORMAT_XRGB1555, DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888, + DRM_FORMAT_XRGB2101010, }; static const struct jz_soc_info jz4740_soc_info = { diff --git a/drivers/gpu/drm/ingenic/ingenic-drm.h b/drivers/gpu/drm/ingenic/ingenic-drm.h index df99f0f75d39..f05e18e6b6fa 100644 --- a/drivers/gpu/drm/ingenic/ingenic-drm.h +++ b/drivers/gpu/drm/ingenic/ingenic-drm.h @@ -124,6 +124,7 @@ #define JZ_LCD_CTRL_BPP_8 0x3 #define JZ_LCD_CTRL_BPP_15_16 0x4 #define JZ_LCD_CTRL_BPP_18_24 0x5 +#define JZ_LCD_CTRL_BPP_30 0x7 #define JZ_LCD_CTRL_BPP_MASK (JZ_LCD_CTRL_RGB555 | 0x7) #define JZ_LCD_CMD_SOF_IRQ BIT(31) -- 2.11.0