From bbfb6f132abc032229f5c1f25e6e959861c6f759 Mon Sep 17 00:00:00 2001 From: Tom Musta Date: Wed, 25 Sep 2013 17:42:46 +1000 Subject: [PATCH] target-ppc: Little Endian Correction to Load/Store Vector Element The Load Vector Element (lve*x) and Store Vector Element (stve*x) instructions not only byte-swap in Little Endian mode, they also invert the element that is accessed. For example, the RTL for lvehx contains this: eb <-- EA[60:63] if Big-Endian byte ordering then VRT[8*eb:8*eb+15] <-- MEM(EA,2) else VRT[112-(8*eb):127-(8*eb)] <-- MEM(EA,2) This patch adds the element inversion, as described in the last line of the RTL. Signed-off-by: Tom Musta Reviewed-by: Anton Blanchard Signed-off-by: Alexander Graf --- target-ppc/mem_helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target-ppc/mem_helper.c b/target-ppc/mem_helper.c index d8e63ca7d2..f35ed037c7 100644 --- a/target-ppc/mem_helper.c +++ b/target-ppc/mem_helper.c @@ -212,6 +212,7 @@ target_ulong helper_lscbx(CPUPPCState *env, target_ulong addr, uint32_t reg, int index = (addr & 0xf) >> sh; \ \ if (msr_le) { \ + index = n_elems - index - 1; \ r->element[LO_IDX ? index : (adjust - index)] = \ swap(access(env, addr)); \ } else { \ @@ -236,6 +237,7 @@ LVE(lvewx, cpu_ldl_data, bswap32, u32) int index = (addr & 0xf) >> sh; \ \ if (msr_le) { \ + index = n_elems - index - 1; \ access(env, addr, swap(r->element[LO_IDX ? index : \ (adjust - index)])); \ } else { \ -- 2.11.0