From bc63c99ef8184aaf2f6ea488e5fc9cfa391b871e Mon Sep 17 00:00:00 2001 From: Dave Jiang Date: Mon, 4 Sep 2023 14:28:04 +0100 Subject: [PATCH] hw/pci-bridge/cxl_upstream: Fix bandwidth entry base unit for SSLBIS MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit According to ACPI spec 6.5 5.2.28.4 System Locality Latency and Bandwidth Information Structure, if the "Entry Base Unit" is 1024 for BW and the matrix entry has the value of 100, the BW is 100 GB/s. So the entry_base_unit should be changed from 1000 to 1024 given the comment notes it's 16GB/s for .latency_bandwidth. Fixes: 882877fc359d ("hw/pci-bridge/cxl-upstream: Add a CDAT table access DOE") Signed-off-by: Dave Jiang Signed-off-by: Jonathan Cameron Reviewed-by: Fan Ni Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Michael Tokarev --- hw/pci-bridge/cxl_upstream.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/pci-bridge/cxl_upstream.c b/hw/pci-bridge/cxl_upstream.c index 9159f48a8c..2b9cf0cc97 100644 --- a/hw/pci-bridge/cxl_upstream.c +++ b/hw/pci-bridge/cxl_upstream.c @@ -262,7 +262,7 @@ static int build_cdat_table(CDATSubHeader ***cdat_table, void *priv) .length = sslbis_size, }, .data_type = HMATLB_DATA_TYPE_ACCESS_BANDWIDTH, - .entry_base_unit = 1000, + .entry_base_unit = 1024, }, }; -- 2.11.0