From be0a4faf35fa49d22dfd6a11ed858610881affde Mon Sep 17 00:00:00 2001 From: Bharata B Rao Date: Wed, 23 Nov 2016 17:07:14 +0530 Subject: [PATCH] target-ppc: Add xscmpoqp and xscmpuqp instructions xscmpoqp - VSX Scalar Compare Ordered Quad-Precision xscmpuqp - VSX Scalar Compare Unordered Quad-Precision Signed-off-by: Bharata B Rao Signed-off-by: Nikunj A Dadhania Signed-off-by: David Gibson --- target/ppc/fpu_helper.c | 54 +++++++++++++++++++++++++++++++++++++ target/ppc/helper.h | 2 ++ target/ppc/translate/vsx-impl.inc.c | 2 ++ target/ppc/translate/vsx-ops.inc.c | 2 ++ 4 files changed, 60 insertions(+) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 8bffafb57e..696f537371 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -2519,6 +2519,60 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ VSX_SCALAR_CMP(xscmpodp, 1) VSX_SCALAR_CMP(xscmpudp, 0) +#define VSX_SCALAR_CMPQ(op, ordered) \ +void helper_##op(CPUPPCState *env, uint32_t opcode) \ +{ \ + ppc_vsr_t xa, xb; \ + uint32_t cc = 0; \ + bool vxsnan_flag = false, vxvc_flag = false; \ + float128 a, b; \ + \ + helper_reset_fpstatus(env); \ + getVSR(rA(opcode) + 32, &xa, env); \ + getVSR(rB(opcode) + 32, &xb, env); \ + \ + a = make_float128(xa.VsrD(0), xa.VsrD(1)); \ + b = make_float128(xb.VsrD(0), xb.VsrD(1)); \ + \ + if (float128_is_signaling_nan(a, &env->fp_status) || \ + float128_is_signaling_nan(b, &env->fp_status)) { \ + vxsnan_flag = true; \ + cc = CRF_SO; \ + if (fpscr_ve == 0 && ordered) { \ + vxvc_flag = true; \ + } \ + } else if (float128_is_quiet_nan(a, &env->fp_status) || \ + float128_is_quiet_nan(b, &env->fp_status)) { \ + cc = CRF_SO; \ + if (ordered) { \ + vxvc_flag = true; \ + } \ + } \ + if (vxsnan_flag) { \ + float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \ + } \ + if (vxvc_flag) { \ + float_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0); \ + } \ + \ + if (float128_lt(a, b, &env->fp_status)) { \ + cc |= CRF_LT; \ + } else if (!float128_le(a, b, &env->fp_status)) { \ + cc |= CRF_GT; \ + } else { \ + cc |= CRF_EQ; \ + } \ + \ + env->fpscr &= ~(0x0F << FPSCR_FPRF); \ + env->fpscr |= cc << FPSCR_FPRF; \ + env->crf[BF(opcode)] = cc; \ + \ + float_check_status(env); \ +} + +VSX_SCALAR_CMPQ(xscmpoqp, 1) +VSX_SCALAR_CMPQ(xscmpuqp, 0) + /* VSX_MAX_MIN - VSX floating point maximum/minimum * name - instruction mnemonic * op - operation (max or min) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 042b8c1310..125d6c5031 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -403,6 +403,8 @@ DEF_HELPER_2(xscmpexpdp, void, env, i32) DEF_HELPER_2(xscmpexpqp, void, env, i32) DEF_HELPER_2(xscmpodp, void, env, i32) DEF_HELPER_2(xscmpudp, void, env, i32) +DEF_HELPER_2(xscmpoqp, void, env, i32) +DEF_HELPER_2(xscmpuqp, void, env, i32) DEF_HELPER_2(xsmaxdp, void, env, i32) DEF_HELPER_2(xsmindp, void, env, i32) DEF_HELPER_2(xscvdpsp, void, env, i32) diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c index 5206258f02..ed9588ebfe 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -628,6 +628,8 @@ GEN_VSX_HELPER_2(xscmpexpdp, 0x0C, 0x07, 0, PPC2_ISA300) GEN_VSX_HELPER_2(xscmpexpqp, 0x04, 0x05, 0, PPC2_ISA300) GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX) GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX) +GEN_VSX_HELPER_2(xscmpoqp, 0x04, 0x04, 0, PPC2_VSX) +GEN_VSX_HELPER_2(xscmpuqp, 0x04, 0x14, 0, PPC2_VSX) GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX) GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX) GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX) diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c index 2468ee9ff9..7f095277b7 100644 --- a/target/ppc/translate/vsx-ops.inc.c +++ b/target/ppc/translate/vsx-ops.inc.c @@ -126,6 +126,8 @@ GEN_XX3FORM(xscmpexpdp, 0x0C, 0x07, PPC2_ISA300), GEN_VSX_XFORM_300(xscmpexpqp, 0x04, 0x05, 0x00600001), GEN_XX2IFORM(xscmpodp, 0x0C, 0x05, PPC2_VSX), GEN_XX2IFORM(xscmpudp, 0x0C, 0x04, PPC2_VSX), +GEN_VSX_XFORM_300(xscmpoqp, 0x04, 0x04, 0x00600001), +GEN_VSX_XFORM_300(xscmpuqp, 0x04, 0x14, 0x00600001), GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX), GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX), GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX), -- 2.11.0