From c1fe3e3b330d9404530abc2fbbd0f6d1fa64ce01 Mon Sep 17 00:00:00 2001 From: Reed Kotler Date: Wed, 18 Sep 2013 22:46:09 +0000 Subject: [PATCH] Fix two issues regarding Got pointer (GP) setup. 1) make sure that the first two instructions of the sequence cannot separate from each other. The linker requires that they be sequential. If they get separated, it can still work but it will not work in all cases because the first of the instructions mostly involves the hi part of the pc relative offset and that part changes slowly. You would have to be at the right boundary for this to matter. 2) make sure that this sequence begins on a longword boundary. There appears to be a bug in binutils which makes some of these calculations get messed up if the instruction sequence does not begin on a longword boundary. This is being investigated with the appropriate binutils folks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190966 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/Mips16ISelDAGToDAG.cpp | 9 +++++---- lib/Target/Mips/Mips16InstrInfo.td | 9 +++++++++ test/CodeGen/Mips/helloworld.ll | 22 ++++++++++++---------- 3 files changed, 26 insertions(+), 14 deletions(-) diff --git a/lib/Target/Mips/Mips16ISelDAGToDAG.cpp b/lib/Target/Mips/Mips16ISelDAGToDAG.cpp index 0caa27753aa..4948f40734c 100644 --- a/lib/Target/Mips/Mips16ISelDAGToDAG.cpp +++ b/lib/Target/Mips/Mips16ISelDAGToDAG.cpp @@ -80,10 +80,11 @@ void Mips16DAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) { V1 = RegInfo.createVirtualRegister(RC); V2 = RegInfo.createVirtualRegister(RC); - BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmX16), V0) - .addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI); - BuildMI(MBB, I, DL, TII.get(Mips::AddiuRxPcImmX16), V1) - .addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO); + BuildMI(MBB, I, DL, TII.get(Mips::GotPrologue16), V0). + addReg(V1, RegState::Define). + addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI). + addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO); + BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16); BuildMI(MBB, I, DL, TII.get(Mips::AdduRxRyRz16), GlobalBaseReg) .addReg(V1).addReg(V2); diff --git a/lib/Target/Mips/Mips16InstrInfo.td b/lib/Target/Mips/Mips16InstrInfo.td index dd0cea6a106..c9840b3f273 100644 --- a/lib/Target/Mips/Mips16InstrInfo.td +++ b/lib/Target/Mips/Mips16InstrInfo.td @@ -768,6 +768,10 @@ def LiRxImm16: FRI16_ins<0b01101, "li", IIAlu>; // def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>; +def LiRxImmAlignX16: FEXT_RI16_ins<0b01101, ".align 2\n\tli", IIAlu> { + let isCodeGenOnly = 1; +} + // // Format: LW ry, offset(rx) MIPS16e // Purpose: Load Word (Extended) @@ -1808,3 +1812,8 @@ def : Mips16Pat<(i32 (extloadi16 addr16:$src)), def: Mips16Pat<(trap), (Break16)>; +def GotPrologue16: + MipsPseudo16< + (outs CPU16Regs:$rh, CPU16Regs:$rl), + (ins simm16:$immHi, simm16:$immLo), + ".align 2\n\tli\t$rh, $immHi\n\taddiu\t$rl, $$pc, $immLo\n ",[]> ; diff --git a/test/CodeGen/Mips/helloworld.ll b/test/CodeGen/Mips/helloworld.ll index 83c88ae3441..058a041c16a 100644 --- a/test/CodeGen/Mips/helloworld.ll +++ b/test/CodeGen/Mips/helloworld.ll @@ -1,11 +1,11 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=C1 -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=C2 -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=PE -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=static -O3 < %s | FileCheck %s -check-prefix=ST1 -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=static -O3 < %s | FileCheck %s -check-prefix=ST2 +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=C1 +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=C2 +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=PE +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=static -O3 < %s | FileCheck %s -check-prefix=ST1 +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=static -O3 < %s | FileCheck %s -check-prefix=ST2 ; -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=SR -; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=SR32 +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=SR +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=SR32 @.str = private unnamed_addr constant [13 x i8] c"hello world\0A\00", align 1 @@ -26,9 +26,11 @@ entry: ; SR32: .set nomacro ; SR32: .set noat ; SR: save $ra, $s0, $s1, $s2, [[FS:[0-9]+]] -; PE: li $[[T1:[0-9]+]], %hi(_gp_disp) -; PE: addiu $[[T2:[0-9]+]], $pc, %lo(_gp_disp) -; PE: sll $[[T3:[0-9]+]], $[[T1]], 16 +; PE: .ent main +; PE: .align 2 +; PE-NEXT: li $[[T1:[0-9]+]], %hi(_gp_disp) +; PE-NEXT: addiu $[[T2:[0-9]+]], $pc, %lo(_gp_disp) +; PE: sll $[[T3:[0-9]+]], $[[T1]], 16 ; C1: lw ${{[0-9]+}}, %got($.str)(${{[0-9]+}}) ; C2: lw ${{[0-9]+}}, %call16(printf)(${{[0-9]+}}) ; C1: addiu ${{[0-9]+}}, %lo($.str) -- 2.11.0