From c264a07cd68c2da1f7bebd1afe2b867fc9906924 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Fri, 8 Dec 2017 15:17:32 +0000 Subject: [PATCH] [X86][AVX512] Tag AVX512_512_SEXT_MASK_* instructions scheduler classes Match VPTERNLOG which these pseudos will eventually alias to git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320154 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86InstrAVX512.td | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/Target/X86/X86InstrAVX512.td b/lib/Target/X86/X86InstrAVX512.td index ccbedf1df63..197e7f0fc55 100644 --- a/lib/Target/X86/X86InstrAVX512.td +++ b/lib/Target/X86/X86InstrAVX512.td @@ -453,7 +453,7 @@ def AVX512_512_SETALLONES : I<0, Pseudo, (outs VR512:$dst), (ins), "", // Alias instructions that allow VPTERNLOG to be used with a mask to create // a mix of all ones and all zeros elements. This is done this way to force // the same register to be used as input for all three sources. -let isPseudo = 1, Predicates = [HasAVX512] in { +let isPseudo = 1, Predicates = [HasAVX512], SchedRW = [WriteVecALU] in { def AVX512_512_SEXT_MASK_32 : I<0, Pseudo, (outs VR512:$dst), (ins VK16WM:$mask), "", [(set VR512:$dst, (vselect (v16i1 VK16WM:$mask), -- 2.11.0