From c26d6b58610520ba76c1cd4c5c1fedd105ba4dad Mon Sep 17 00:00:00 2001 From: Bhalchandra Gajare Date: Thu, 27 Oct 2016 14:38:01 -0700 Subject: [PATCH] ASoC: wcd934x: fix default value for FLL threshold The default value of CPE FLL threshold register needs to be updated to 0x20 as per the hardware specification. Change fixes this by adding this register to the codec register defaults. CRs-Fixed: 1083199 Change-Id: Ib19d78f0834803c75b255ee3a119e043ffb8a988 Signed-off-by: Bhalchandra Gajare --- sound/soc/codecs/wcd934x/wcd934x.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sound/soc/codecs/wcd934x/wcd934x.c b/sound/soc/codecs/wcd934x/wcd934x.c index 30c23df444d6..65386b1786aa 100644 --- a/sound/soc/codecs/wcd934x/wcd934x.c +++ b/sound/soc/codecs/wcd934x/wcd934x.c @@ -8005,6 +8005,7 @@ static const struct tavil_reg_mask_val tavil_codec_reg_defaults[] = { {WCD934X_HPH_OCP_CTL, 0xFF, 0x3A}, /* OCP current limit */ {WCD934X_HPH_L_TEST, 0x01, 0x01}, {WCD934X_HPH_R_TEST, 0x01, 0x01}, + {WCD934X_CPE_FLL_CONFIG_CTL_2, 0xFF, 0x20}, }; static const struct tavil_reg_mask_val tavil_codec_reg_init_1_1_val[] = { -- 2.11.0