From c2afd0ce7b6f5f6a1bba6301929e3702cb176fbe Mon Sep 17 00:00:00 2001
From: Zvi Rackover <zvi.rackover@intel.com>
Date: Thu, 6 Oct 2016 10:04:00 +0000
Subject: [PATCH] Add test-cases which demontrate pr30561

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283436 91177308-0d34-0410-b5e6-96231b3b80d8
---
 test/CodeGen/X86/avx512-select.ll | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/test/CodeGen/X86/avx512-select.ll b/test/CodeGen/X86/avx512-select.ll
index 80026e5e79a..aedb69db2d6 100644
--- a/test/CodeGen/X86/avx512-select.ll
+++ b/test/CodeGen/X86/avx512-select.ll
@@ -158,3 +158,29 @@ define i64 @pr30249() {
   %v = select i1 undef , i64 1, i64 2
   ret i64 %v
 }
+
+define double @pr30561_f64(double %a, double %b, i1 %c) {
+; CHECK-LABEL: pr30561_f64:
+; CHECK:       ## BB#0:
+; CHECK-NEXT:    testb $1, %dil
+; CHECK-NEXT:    jne LBB11_2
+; CHECK-NEXT:  ## BB#1:
+; CHECK-NEXT:    vmovaps %xmm1, %xmm0
+; CHECK-NEXT:  LBB11_2:
+; CHECK-NEXT:    retq
+  %cond = select i1 %c, double %a, double %b
+  ret double %cond
+}
+
+define float @pr30561_f32(float %a, float %b, i1 %c) {
+; CHECK-LABEL: pr30561_f32:
+; CHECK:       ## BB#0:
+; CHECK-NEXT:    testb $1, %dil
+; CHECK-NEXT:    jne LBB12_2
+; CHECK-NEXT:  ## BB#1:
+; CHECK-NEXT:    vmovaps %xmm1, %xmm0
+; CHECK-NEXT:  LBB12_2:
+; CHECK-NEXT:    retq
+  %cond = select i1 %c, float %a, float %b
+  ret float %cond
+}
-- 
2.11.0