From c6d9c4ee81a35d0fca5ba87358167c4b872ca50b Mon Sep 17 00:00:00 2001 From: Zoran Jovanovic Date: Mon, 12 Oct 2015 16:07:25 +0000 Subject: [PATCH] [mips][micromips] Initial support for micrmomips DSP instructions and addu.qb implementation Differential Revision: http://reviews.llvm.org/D12798 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250058 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 1 + lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp | 4 ++++ lib/Target/Mips/MicroMipsDSPInstrFormats.td | 28 ++++++++++++++++++++++ lib/Target/Mips/MicroMipsDSPInstrInfo.td | 19 +++++++++++++++ lib/Target/Mips/Mips.td | 3 +++ lib/Target/Mips/MipsDSPInstrFormats.td | 21 +++++++++++++++- lib/Target/Mips/MipsDSPInstrInfo.td | 2 +- lib/Target/Mips/MipsInstrInfo.td | 4 ++++ lib/Target/Mips/MipsSubtarget.cpp | 4 ++-- lib/Target/Mips/MipsSubtarget.h | 5 ++-- test/MC/Disassembler/Mips/micromips-dsp/valid.txt | 4 ++++ test/MC/Mips/micromips-dsp/valid.s | 5 ++++ 12 files changed, 94 insertions(+), 6 deletions(-) create mode 100644 lib/Target/Mips/MicroMipsDSPInstrFormats.td create mode 100644 lib/Target/Mips/MicroMipsDSPInstrInfo.td create mode 100644 test/MC/Disassembler/Mips/micromips-dsp/valid.txt create mode 100644 test/MC/Mips/micromips-dsp/valid.s diff --git a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 317c2c6ad2a..70cc6a614e2 100644 --- a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -483,6 +483,7 @@ public: bool hasDSP() const { return STI.getFeatureBits()[Mips::FeatureDSP]; } bool hasDSPR2() const { return STI.getFeatureBits()[Mips::FeatureDSPR2]; } + bool hasDSPR3() const { return STI.getFeatureBits()[Mips::FeatureDSPR3]; } bool hasMSA() const { return STI.getFeatureBits()[Mips::FeatureMSA]; } bool hasCnMips() const { return (STI.getFeatureBits()[Mips::FeatureCnMips]); diff --git a/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp b/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp index 2e50560a3f9..1d06860bdf9 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp +++ b/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp @@ -190,6 +190,10 @@ encodeInstruction(const MCInst &MI, raw_ostream &OS, else NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips); + // Check whether it is Dsp instruction. + if (NewOpcode == -1) + NewOpcode = Mips::Dsp2MicroMips(Opcode, Mips::Arch_mmdsp); + if (NewOpcode != -1) { if (Fixups.size() > N) Fixups.pop_back(); diff --git a/lib/Target/Mips/MicroMipsDSPInstrFormats.td b/lib/Target/Mips/MicroMipsDSPInstrFormats.td new file mode 100644 index 00000000000..a748f0df745 --- /dev/null +++ b/lib/Target/Mips/MicroMipsDSPInstrFormats.td @@ -0,0 +1,28 @@ +//===-- MicroMipsDSPInstrFormats.td - Instruction Formats --*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +class MMDSPInst + : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, PredicateControl { + let InsnPredicates = [HasDSP]; + string BaseOpcode = opstr; + string Arch = "mmdsp"; + let DecoderNamespace = "MicroMips"; +} + +class POOL32A_3R_FMT op> : MMDSPInst { + bits<5> rd; + bits<5> rs; + bits<5> rt; + + let Inst{31-26} = 0b000000; + let Inst{25-21} = rt; + let Inst{20-16} = rs; + let Inst{15-11} = rd; + let Inst{10-0} = op; +} diff --git a/lib/Target/Mips/MicroMipsDSPInstrInfo.td b/lib/Target/Mips/MicroMipsDSPInstrInfo.td new file mode 100644 index 00000000000..e107de87e64 --- /dev/null +++ b/lib/Target/Mips/MicroMipsDSPInstrInfo.td @@ -0,0 +1,19 @@ +//===- MicroMipsDSPInstrInfo.td - Micromips DSP instructions -*- tablegen *-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes MicroMips DSP instructions. +// +//===----------------------------------------------------------------------===// + +// Instruction encoding. +class ADDU_QB_MM_ENC : POOL32A_3R_FMT<0b00011001101>; + +// Instruction defs. +// MIPS DSP Rev 1 +def ADDU_QB_MM : DspMMRel, ADDU_QB_MM_ENC, ADDU_QB_DESC, ISA_MICROMIPS; diff --git a/lib/Target/Mips/Mips.td b/lib/Target/Mips/Mips.td index d46356ab121..57c74bad9a7 100644 --- a/lib/Target/Mips/Mips.td +++ b/lib/Target/Mips/Mips.td @@ -154,6 +154,9 @@ def FeatureMips16 : SubtargetFeature<"mips16", "InMips16Mode", "true", def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">; def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true", "Mips DSP-R2 ASE", [FeatureDSP]>; +def FeatureDSPR3 + : SubtargetFeature<"dspr3", "HasDSPR3", "true", "Mips DSP-R3 ASE", + [ FeatureDSP, FeatureDSPR2 ]>; def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">; diff --git a/lib/Target/Mips/MipsDSPInstrFormats.td b/lib/Target/Mips/MipsDSPInstrFormats.td index b5d52ced9d3..a490d877b79 100644 --- a/lib/Target/Mips/MipsDSPInstrFormats.td +++ b/lib/Target/Mips/MipsDSPInstrFormats.td @@ -7,10 +7,26 @@ // //===----------------------------------------------------------------------===// +class DspMMRel; + +def Dsp2MicroMips : InstrMapping { + let FilterClass = "DspMMRel"; + // Instructions with the same BaseOpcode and isNVStore values form a row. + let RowFields = ["BaseOpcode"]; + // Instructions with the same predicate sense form a column. + let ColFields = ["Arch"]; + // The key column is the unpredicated instructions. + let KeyCol = ["dsp"]; + // Value columns are PredSense=true and PredSense=false + let ValueCols = [["dsp"], ["mmdsp"]]; +} + def HasDSP : Predicate<"Subtarget->hasDSP()">, AssemblerPredicate<"FeatureDSP">; def HasDSPR2 : Predicate<"Subtarget->hasDSPR2()">, AssemblerPredicate<"FeatureDSPR2">; +def HasDSPR3 : Predicate<"Subtarget->hasDSPR3()">, + AssemblerPredicate<"FeatureDSPR3">; // Fields. class Field6 val> { @@ -20,8 +36,11 @@ class Field6 val> { def SPECIAL3_OPCODE : Field6<0b011111>; def REGIMM_OPCODE : Field6<0b000001>; -class DSPInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> { +class DSPInst + : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> { let Predicates = [HasDSP]; + string BaseOpcode = opstr; + string Arch = "dsp"; } class PseudoDSP pattern, diff --git a/lib/Target/Mips/MipsDSPInstrInfo.td b/lib/Target/Mips/MipsDSPInstrInfo.td index d2683840445..c372d79af79 100644 --- a/lib/Target/Mips/MipsDSPInstrInfo.td +++ b/lib/Target/Mips/MipsDSPInstrInfo.td @@ -1072,7 +1072,7 @@ def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE