From ccd873f0c0574567003a652e826ac64782e7fe9a Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Tue, 9 Jul 2019 03:20:33 +0000 Subject: [PATCH] [AMDGPU] Added td definitions for HW regs Infrastructure work for future commit. NFC. Differential Revision: https://reviews.llvm.org/D64370 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365432 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AMDGPU/SIInstrInfo.td | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/lib/Target/AMDGPU/SIInstrInfo.td b/lib/Target/AMDGPU/SIInstrInfo.td index 4ca4d36847f..11393c9d30a 100644 --- a/lib/Target/AMDGPU/SIInstrInfo.td +++ b/lib/Target/AMDGPU/SIInstrInfo.td @@ -1159,6 +1159,31 @@ def TRAPID{ int LLVM_DEBUG_TRAP = 3; } +def HWREG { + int MODE = 1; + int STATUS = 2; + int TRAPSTS = 3; + int HW_ID = 4; + int GPR_ALLOC = 5; + int LDS_ALLOC = 6; + int IB_STS = 7; + int MEM_BASES = 15; + int TBA_LO = 16; + int TBA_HI = 17; + int TMA_LO = 18; + int TMA_HI = 19; + int FLAT_SCR_LO = 20; + int FLAT_SCR_HI = 21; + int XNACK_MASK = 22; + int POPS_PACKER = 25; +} + +class getHwRegImm { + int ret = !or(Reg, + !or(!shl(Offset, 6), + !shl(!add(Size, -1), 11))); +} + //===----------------------------------------------------------------------===// // // SI Instruction multiclass helpers. -- 2.11.0