From ce9c45a60ed51ddb27bd969bdc61336f18121a07 Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Fri, 17 Jan 2020 14:13:28 -0600 Subject: [PATCH] intel/blorp: Plumb deref block size through to 3DSTATE_SF Cc: "20.0" mesa-stable@lists.freedesktop.org Reviewed-by: Kenneth Graunke Part-of: --- src/intel/blorp/blorp_genX_exec.h | 16 ++++++++++------ src/mesa/drivers/dri/i965/gen4_blorp_exec.h | 2 +- 2 files changed, 11 insertions(+), 7 deletions(-) diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h index 3cd2ce6d048..0b5ce029f4c 100644 --- a/src/intel/blorp/blorp_genX_exec.h +++ b/src/intel/blorp/blorp_genX_exec.h @@ -189,7 +189,8 @@ _blorp_combine_address(struct blorp_batch *batch, void *location, */ static void emit_urb_config(struct blorp_batch *batch, - const struct blorp_params *params) + const struct blorp_params *params, + enum gen_urb_deref_block_size *deref_block_size) { /* Once vertex fetcher has written full VUE entries with complete * header the space requirement is as follows per vertex (in bytes): @@ -218,7 +219,8 @@ emit_urb_config(struct blorp_batch *batch, unsigned entries[4], start[4]; gen_get_urb_config(batch->blorp->compiler->devinfo, blorp_get_l3_config(batch), - false, false, entry_size, entries, start, NULL); + false, false, entry_size, + entries, start, deref_block_size); #if GEN_GEN == 7 && !GEN_IS_HASWELL /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1: @@ -685,7 +687,8 @@ blorp_emit_vs_config(struct blorp_batch *batch, static void blorp_emit_sf_config(struct blorp_batch *batch, - const struct blorp_params *params) + const struct blorp_params *params, + enum gen_urb_deref_block_size urb_deref_block_size) { const struct brw_wm_prog_data *prog_data = params->wm_prog_data; @@ -712,7 +715,7 @@ blorp_emit_sf_config(struct blorp_batch *batch, blorp_emit(batch, GENX(3DSTATE_SF), sf) { #if GEN_GEN >= 12 - sf.DerefBlockSize = PerPolyDerefMode; + sf.DerefBlockSize = urb_deref_block_size; #endif } @@ -1255,7 +1258,8 @@ blorp_emit_pipeline(struct blorp_batch *batch, uint32_t color_calc_state_offset; uint32_t depth_stencil_state_offset; - emit_urb_config(batch, params); + enum gen_urb_deref_block_size urb_deref_block_size; + emit_urb_config(batch, params, &urb_deref_block_size); if (params->wm_prog_data) { blend_state_offset = blorp_emit_blend_state(batch, params); @@ -1336,7 +1340,7 @@ blorp_emit_pipeline(struct blorp_batch *batch, clip.PerspectiveDivideDisable = true; } - blorp_emit_sf_config(batch, params); + blorp_emit_sf_config(batch, params, urb_deref_block_size); blorp_emit_ps_config(batch, params); blorp_emit_cc_viewport(batch); diff --git a/src/mesa/drivers/dri/i965/gen4_blorp_exec.h b/src/mesa/drivers/dri/i965/gen4_blorp_exec.h index 0edc518fa35..d279094a5a2 100644 --- a/src/mesa/drivers/dri/i965/gen4_blorp_exec.h +++ b/src/mesa/drivers/dri/i965/gen4_blorp_exec.h @@ -178,7 +178,7 @@ blorp_emit_pipeline(struct blorp_batch *batch, assert(batch->blorp->driver_ctx == batch->driver_batch); struct brw_context *brw = batch->driver_batch; - emit_urb_config(batch, params); + emit_urb_config(batch, params, NULL); blorp_emit(batch, GENX(3DSTATE_PIPELINED_POINTERS), pp) { pp.PointertoVSState = blorp_emit_vs_state(batch); -- 2.11.0