From cf4dd91f292ab569d7b3c3ec480b448f0360881a Mon Sep 17 00:00:00 2001 From: astoria-d Date: Sat, 27 Aug 2016 11:22:03 +0900 Subject: [PATCH] vram latch addr output timing changed --- de1_nes/ppu/ppu_registers.vhd | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/de1_nes/ppu/ppu_registers.vhd b/de1_nes/ppu/ppu_registers.vhd index 6764f16..338ebfd 100644 --- a/de1_nes/ppu/ppu_registers.vhd +++ b/de1_nes/ppu/ppu_registers.vhd @@ -103,8 +103,8 @@ component tri_state_buffer ); end component; -signal d_in, q_out : std_logic_vector(13 downto 0); -signal we_n, oe_n : std_logic; +signal d_in : std_logic_vector(13 downto 0); +signal we_n, oe_n : std_logic; begin dbg_vl_we_n <= we_n; @@ -115,8 +115,6 @@ begin oe_n <= '0' when ale = '0' else '1'; out_reg_inst : d_flip_flop generic map (14) - port map (clk, rst_n, '1', we_n, d_in, q_out); - out_tss_inst : tri_state_buffer generic map (14) - port map (oe_n, q_out, v_addr); + port map (clk, rst_n, '1', we_n, d_in, v_addr); end rtl; -- 2.11.0