From cfe86292ec71569d9525815a2ad3883babb03b1b Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Mon, 27 Jan 2020 20:26:04 +0200 Subject: [PATCH] drm/i915/combo_phy: use intel_de_*() functions for register access The implicit "dev_priv" local variable use has been a long-standing pain point in the register access macros I915_READ(), I915_WRITE(), POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW(). Replace them with the corresponding new display engine register accessors intel_de_read(), intel_de_write(), intel_de_posting_read(), intel_de_read_fw(), and intel_de_write_fw(). No functional changes. Generated using the following semantic patch: @@ expression REG, OFFSET; @@ - I915_READ(REG) + intel_de_read(dev_priv, REG) @@ expression REG, OFFSET; @@ - POSTING_READ(REG) + intel_de_posting_read(dev_priv, REG) @@ expression REG, OFFSET; @@ - I915_WRITE(REG, OFFSET) + intel_de_write(dev_priv, REG, OFFSET) @@ expression REG; @@ - I915_READ_FW(REG) + intel_de_read_fw(dev_priv, REG) @@ expression REG, OFFSET; @@ - I915_WRITE_FW(REG, OFFSET) + intel_de_write_fw(dev_priv, REG, OFFSET) Acked-by: Chris Wilson Acked-by: Rodrigo Vivi Acked-by: Joonas Lahtinen Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/48b61928049d3be6541a16789622b4479ea26a84.1580149467.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/display/intel_combo_phy.c | 66 +++++++++++++------------- 1 file changed, 33 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c index ec63c2657923..11f80f15cb4d 100644 --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c @@ -48,7 +48,7 @@ cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy) const struct cnl_procmon *procmon; u32 val; - val = I915_READ(ICL_PORT_COMP_DW3(phy)); + val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy)); switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) { default: MISSING_CASE(val); @@ -81,20 +81,20 @@ static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv, procmon = cnl_get_procmon_ref_values(dev_priv, phy); - val = I915_READ(ICL_PORT_COMP_DW1(phy)); + val = intel_de_read(dev_priv, ICL_PORT_COMP_DW1(phy)); val &= ~((0xff << 16) | 0xff); val |= procmon->dw1; - I915_WRITE(ICL_PORT_COMP_DW1(phy), val); + intel_de_write(dev_priv, ICL_PORT_COMP_DW1(phy), val); - I915_WRITE(ICL_PORT_COMP_DW9(phy), procmon->dw9); - I915_WRITE(ICL_PORT_COMP_DW10(phy), procmon->dw10); + intel_de_write(dev_priv, ICL_PORT_COMP_DW9(phy), procmon->dw9); + intel_de_write(dev_priv, ICL_PORT_COMP_DW10(phy), procmon->dw10); } static bool check_phy_reg(struct drm_i915_private *dev_priv, enum phy phy, i915_reg_t reg, u32 mask, u32 expected_val) { - u32 val = I915_READ(reg); + u32 val = intel_de_read(dev_priv, reg); if ((val & mask) != expected_val) { DRM_DEBUG_DRIVER("Combo PHY %c reg %08x state mismatch: " @@ -127,8 +127,8 @@ static bool cnl_verify_procmon_ref_values(struct drm_i915_private *dev_priv, static bool cnl_combo_phy_enabled(struct drm_i915_private *dev_priv) { - return !(I915_READ(CHICKEN_MISC_2) & CNL_COMP_PWR_DOWN) && - (I915_READ(CNL_PORT_COMP_DW0) & COMP_INIT); + return !(intel_de_read(dev_priv, CHICKEN_MISC_2) & CNL_COMP_PWR_DOWN) && + (intel_de_read(dev_priv, CNL_PORT_COMP_DW0) & COMP_INIT); } static bool cnl_combo_phy_verify_state(struct drm_i915_private *dev_priv) @@ -151,20 +151,20 @@ static void cnl_combo_phys_init(struct drm_i915_private *dev_priv) { u32 val; - val = I915_READ(CHICKEN_MISC_2); + val = intel_de_read(dev_priv, CHICKEN_MISC_2); val &= ~CNL_COMP_PWR_DOWN; - I915_WRITE(CHICKEN_MISC_2, val); + intel_de_write(dev_priv, CHICKEN_MISC_2, val); /* Dummy PORT_A to get the correct CNL register from the ICL macro */ cnl_set_procmon_ref_values(dev_priv, PHY_A); - val = I915_READ(CNL_PORT_COMP_DW0); + val = intel_de_read(dev_priv, CNL_PORT_COMP_DW0); val |= COMP_INIT; - I915_WRITE(CNL_PORT_COMP_DW0, val); + intel_de_write(dev_priv, CNL_PORT_COMP_DW0, val); - val = I915_READ(CNL_PORT_CL1CM_DW5); + val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5); val |= CL_POWER_DOWN_ENABLE; - I915_WRITE(CNL_PORT_CL1CM_DW5, val); + intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val); } static void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv) @@ -174,9 +174,9 @@ static void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv) if (!cnl_combo_phy_verify_state(dev_priv)) DRM_WARN("Combo PHY HW state changed unexpectedly.\n"); - val = I915_READ(CHICKEN_MISC_2); + val = intel_de_read(dev_priv, CHICKEN_MISC_2); val |= CNL_COMP_PWR_DOWN; - I915_WRITE(CHICKEN_MISC_2, val); + intel_de_write(dev_priv, CHICKEN_MISC_2, val); } static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv, @@ -184,11 +184,11 @@ static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv, { /* The PHY C added by EHL has no PHY_MISC register */ if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C) - return I915_READ(ICL_PORT_COMP_DW0(phy)) & COMP_INIT; + return intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT; else - return !(I915_READ(ICL_PHY_MISC(phy)) & + return !(intel_de_read(dev_priv, ICL_PHY_MISC(phy)) & ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) && - (I915_READ(ICL_PORT_COMP_DW0(phy)) & COMP_INIT); + (intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT); } static bool ehl_vbt_ddi_d_present(struct drm_i915_private *i915) @@ -294,10 +294,10 @@ void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv, } } - val = I915_READ(ICL_PORT_CL_DW10(phy)); + val = intel_de_read(dev_priv, ICL_PORT_CL_DW10(phy)); val &= ~PWR_DOWN_LN_MASK; val |= lane_mask << PWR_DOWN_LN_SHIFT; - I915_WRITE(ICL_PORT_CL_DW10(phy), val); + intel_de_write(dev_priv, ICL_PORT_CL_DW10(phy), val); } static void icl_combo_phys_init(struct drm_i915_private *dev_priv) @@ -329,7 +329,7 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv) * based on whether our VBT indicates the presence of any * "internal" child devices. */ - val = I915_READ(ICL_PHY_MISC(phy)); + val = intel_de_read(dev_priv, ICL_PHY_MISC(phy)); if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_A) { val &= ~ICL_PHY_MISC_MUX_DDID; @@ -338,24 +338,24 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv) } val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN; - I915_WRITE(ICL_PHY_MISC(phy), val); + intel_de_write(dev_priv, ICL_PHY_MISC(phy), val); skip_phy_misc: cnl_set_procmon_ref_values(dev_priv, phy); if (phy == PHY_A) { - val = I915_READ(ICL_PORT_COMP_DW8(phy)); + val = intel_de_read(dev_priv, ICL_PORT_COMP_DW8(phy)); val |= IREFGEN; - I915_WRITE(ICL_PORT_COMP_DW8(phy), val); + intel_de_write(dev_priv, ICL_PORT_COMP_DW8(phy), val); } - val = I915_READ(ICL_PORT_COMP_DW0(phy)); + val = intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)); val |= COMP_INIT; - I915_WRITE(ICL_PORT_COMP_DW0(phy), val); + intel_de_write(dev_priv, ICL_PORT_COMP_DW0(phy), val); - val = I915_READ(ICL_PORT_CL_DW5(phy)); + val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); val |= CL_POWER_DOWN_ENABLE; - I915_WRITE(ICL_PORT_CL_DW5(phy), val); + intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val); } } @@ -379,14 +379,14 @@ static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv) if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C) goto skip_phy_misc; - val = I915_READ(ICL_PHY_MISC(phy)); + val = intel_de_read(dev_priv, ICL_PHY_MISC(phy)); val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN; - I915_WRITE(ICL_PHY_MISC(phy), val); + intel_de_write(dev_priv, ICL_PHY_MISC(phy), val); skip_phy_misc: - val = I915_READ(ICL_PORT_COMP_DW0(phy)); + val = intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)); val &= ~COMP_INIT; - I915_WRITE(ICL_PORT_COMP_DW0(phy), val); + intel_de_write(dev_priv, ICL_PORT_COMP_DW0(phy), val); } } -- 2.11.0