From d018c5d7470904b3a559f0e74d082b227a05c46f Mon Sep 17 00:00:00 2001 From: Lei Huang Date: Thu, 12 Apr 2018 18:00:14 +0000 Subject: [PATCH] [Power9]Legalize and emit code for converting (Un)Signed DWord to Quad-Precision Legalize and emit code for: * xscvsdqp * xscvudqp Differential Revision: https://reviews.llvm.org/D45230 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329931 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCISelLowering.cpp | 7 +- lib/Target/PowerPC/PPCInstrVSX.td | 16 ++++ test/CodeGen/PowerPC/f128-conv.ll | 140 +++++++++++++++++++++++++++++++++ 3 files changed, 162 insertions(+), 1 deletion(-) create mode 100644 test/CodeGen/PowerPC/f128-conv.ll diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 53e77ba84e9..bde1af7e16f 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -9409,7 +9409,12 @@ SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG, SDLoc(Op)); case ISD::UINT_TO_FP: - case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG); + case ISD::SINT_TO_FP: + // Conversions to f128 are legal. + if (EnableQuadPrecision && (Op->getValueType(0) == MVT::f128)) + return Op; + return LowerINT_TO_FP(Op, DAG); + case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); // Lower 64-bit shifts. diff --git a/lib/Target/PowerPC/PPCInstrVSX.td b/lib/Target/PowerPC/PPCInstrVSX.td index 04a13e204ac..d84f828949e 100644 --- a/lib/Target/PowerPC/PPCInstrVSX.td +++ b/lib/Target/PowerPC/PPCInstrVSX.td @@ -2512,7 +2512,12 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in { // Convert (Un)Signed DWord -> QP def XSCVSDQP : X_VT5_XO5_VB5_TyVB<63, 10, 836, "xscvsdqp", vfrc, []>; + def : Pat<(f128 (sint_to_fp i64:$src)), + (f128 (XSCVSDQP (COPY_TO_REGCLASS $src, VFRC)))>; + def XSCVUDQP : X_VT5_XO5_VB5_TyVB<63, 2, 836, "xscvudqp", vfrc, []>; + def : Pat<(f128 (uint_to_fp i64:$src)), + (f128 (XSCVUDQP (COPY_TO_REGCLASS $src, VFRC)))>; let UseVSXReg = 1 in { //===--------------------------------------------------------------------===// @@ -3117,6 +3122,17 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in { (COPY_TO_REGCLASS (DFLOADf32 ixaddr:$src), VSFRC)>; def : Pat<(f32 (fpround (f64 (extloadf32 ixaddr:$src)))), (f32 (DFLOADf32 ixaddr:$src))>; + + // Convert (Un)Signed DWord in memory -> QP + def : Pat<(f128 (sint_to_fp (i64 (load xaddr:$src)))), + (f128 (XSCVSDQP (LXSDX xaddr:$src)))>; + def : Pat<(f128 (sint_to_fp (i64 (load ixaddr:$src)))), + (f128 (XSCVSDQP (LXSD ixaddr:$src)))>; + def : Pat<(f128 (uint_to_fp (i64 (load xaddr:$src)))), + (f128 (XSCVUDQP (LXSDX xaddr:$src)))>; + def : Pat<(f128 (uint_to_fp (i64 (load ixaddr:$src)))), + (f128 (XSCVUDQP (LXSD ixaddr:$src)))>; + } // end HasP9Vector, AddedComplexity let Predicates = [HasP9Vector] in { diff --git a/test/CodeGen/PowerPC/f128-conv.ll b/test/CodeGen/PowerPC/f128-conv.ll new file mode 100644 index 00000000000..10eedde245b --- /dev/null +++ b/test/CodeGen/PowerPC/f128-conv.ll @@ -0,0 +1,140 @@ +; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \ +; RUN: -enable-ppc-quad-precision -ppc-vsr-nums-as-vr < %s | FileCheck %s + +@mem = global [5 x i64] [i64 56, i64 63, i64 3, i64 5, i64 6], align 8 +@umem = global [5 x i64] [i64 560, i64 100, i64 34, i64 2, i64 5], align 8 +@swMem = global [5 x i32] [i32 5, i32 2, i32 3, i32 4, i32 0], align 4 + +; Function Attrs: norecurse nounwind +define void @sdwConv2qp(fp128* nocapture %a, i64 %b) { +entry: + %conv = sitofp i64 %b to fp128 + store fp128 %conv, fp128* %a, align 16 + ret void + +; CHECK-LABEL: sdwConv2qp +; CHECK: mtvsrd [[REG:[0-9]+]], 4 +; CHECK-NEXT: xscvsdqp [[CONV:[0-9]+]], [[REG]] +; CHECK-NEXT: stxv [[CONV]], 0(3) +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind +define void @sdwConv2qp_02(fp128* nocapture %a) { +entry: + %0 = load i64, i64* getelementptr inbounds + ([5 x i64], [5 x i64]* @mem, i64 0, i64 2), align 8 + %conv = sitofp i64 %0 to fp128 + store fp128 %conv, fp128* %a, align 16 + ret void + +; CHECK-LABEL: sdwConv2qp_02 +; CHECK: addis [[REG:[0-9]+]], 2, .LC0@toc@ha +; CHECK: ld [[REG]], .LC0@toc@l([[REG]]) +; CHECK: lxsd [[REG0:[0-9]+]], 16([[REG]]) +; CHECK-NEXT: xscvsdqp [[CONV:[0-9]+]], [[REG0]] +; CHECK-NEXT: stxv [[CONV]], 0(3) +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind +define void @sdwConv2qp_03(fp128* nocapture %a, i64* nocapture readonly %b) { +entry: + %0 = load i64, i64* %b, align 8 + %conv = sitofp i64 %0 to fp128 + store fp128 %conv, fp128* %a, align 16 + ret void + +; CHECK-LABEL: sdwConv2qp_03 +; CHECK-NOT: ld +; CHECK: lxsd [[REG0:[0-9]+]], 0(4) +; CHECK-NEXT: xscvsdqp [[CONV:[0-9]+]], [[REG0]] +; CHECK-NEXT: stxv [[CONV]], 0(3) +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind +define void @udwConv2qp(fp128* nocapture %a, i64 %b) { +entry: + %conv = uitofp i64 %b to fp128 + store fp128 %conv, fp128* %a, align 16 + ret void + +; CHECK-LABEL: udwConv2qp +; CHECK: mtvsrd [[REG:[0-9]+]], 4 +; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG]] +; CHECK-NEXT: stxv [[CONV]], 0(3) +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind +define void @udwConv2qp_02(fp128* nocapture %a) { +entry: + %0 = load i64, i64* getelementptr inbounds + ([5 x i64], [5 x i64]* @umem, i64 0, i64 4), align 8 + %conv = uitofp i64 %0 to fp128 + store fp128 %conv, fp128* %a, align 16 + ret void + +; CHECK-LABEL: udwConv2qp_02 +; CHECK: addis [[REG:[0-9]+]], 2, .LC1@toc@ha +; CHECK: ld [[REG]], .LC1@toc@l([[REG]]) +; CHECK: lxsd [[REG0:[0-9]+]], 32([[REG]]) +; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG0]] +; CHECK-NEXT: stxv [[CONV]], 0(3) +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind +define void @udwConv2qp_03(fp128* nocapture %a, i64* nocapture readonly %b) { +entry: + %0 = load i64, i64* %b, align 8 + %conv = uitofp i64 %0 to fp128 + store fp128 %conv, fp128* %a, align 16 + ret void + +; CHECK-LABEL: udwConv2qp_03 +; CHECK-NOT: ld +; CHECK: lxsd [[REG:[0-9]+]], 0(4) +; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG]] +; CHECK-NEXT: stxv [[CONV]], 0(3) +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind +define void @sdwConv2qp_testXForm(fp128* nocapture %sink, + i8* nocapture readonly %a) { +entry: + %add.ptr = getelementptr inbounds i8, i8* %a, i64 3 + %0 = bitcast i8* %add.ptr to i64* + %1 = load i64, i64* %0, align 8 + %conv = sitofp i64 %1 to fp128 + store fp128 %conv, fp128* %sink, align 16 + ret void + +; CHECK-LABEL: sdwConv2qp_testXForm +; CHECK: addi [[REG:[0-9]+]], 4, 3 +; CHECK-NEXT: lxsd [[REG1:[0-9]+]], 0([[REG]]) +; CHECK-NEXT: xscvsdqp [[CONV:[0-9]+]], [[REG1]] +; CHECK-NEXT: stxv [[CONV]], 0(3) +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind +define void @udwConv2qp_testXForm(fp128* nocapture %sink, + i8* nocapture readonly %a) { +entry: + %add.ptr = getelementptr inbounds i8, i8* %a, i64 3 + %0 = bitcast i8* %add.ptr to i64* + %1 = load i64, i64* %0, align 8 + %conv = uitofp i64 %1 to fp128 + store fp128 %conv, fp128* %sink, align 16 + ret void + +; CHECK-LABEL: udwConv2qp_testXForm +; CHECK: addi [[REG:[0-9]+]], 4, 3 +; CHECK-NEXT: lxsd [[REG1:[0-9]+]], 0([[REG]]) +; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG1]] +; CHECK-NEXT: stxv [[CONV]], 0(3) +; CHECK-NEXT: blr +} -- 2.11.0