From d10549743ae65fcc4420a5b07606f97f5cac4bae Mon Sep 17 00:00:00 2001 From: Artyom Skrobov Date: Tue, 8 Dec 2015 19:59:01 +0000 Subject: [PATCH] Fix ARMv4T (Thumb1) epilogue generation Summary: Before ARMv5T, Thumb1 code could not pop PC, as described at D14357 and D14986; so we need the special fixup in the epilogue. Reviewers: jroelofs, qcolombet Subscribers: aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D15126 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255047 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/Thumb1FrameLowering.cpp | 41 ++++++++--- test/CodeGen/ARM/debug-frame.ll | 4 +- test/CodeGen/Thumb/large-stack.ll | 20 +++--- test/CodeGen/Thumb/pop-special-fixup.ll | 60 ---------------- test/CodeGen/Thumb/thumb-shrink-wrapping.ll | 102 ++++++++++++++++++++++++---- 5 files changed, 132 insertions(+), 95 deletions(-) delete mode 100644 test/CodeGen/Thumb/pop-special-fixup.ll diff --git a/lib/Target/ARM/Thumb1FrameLowering.cpp b/lib/Target/ARM/Thumb1FrameLowering.cpp index fd96af6cb6e..8771c68e593 100644 --- a/lib/Target/ARM/Thumb1FrameLowering.cpp +++ b/lib/Target/ARM/Thumb1FrameLowering.cpp @@ -406,9 +406,6 @@ bool Thumb1FrameLowering::needPopSpecialFixUp(const MachineFunction &MF) const { if (AFI->getArgRegsSaveSize()) return true; - // FIXME: this doesn't make sense, and the following patch will remove it. - if (!STI.hasV4TOps()) return false; - // LR cannot be encoded with Thumb1, i.e., it requires a special fix-up. for (const CalleeSavedInfo &CSI : MF.getFrameInfo()->getCalleeSavedInfo()) if (CSI.getReg() == ARM::LR) @@ -532,10 +529,32 @@ bool Thumb1FrameLowering::emitPopSpecialFixUp(MachineBasicBlock &MBB, .addReg(PopReg, RegState::Kill)); } + bool AddBx = false; if (MBBI == MBB.end()) { MachineInstr& Pop = MBB.back(); assert(Pop.getOpcode() == ARM::tPOP); Pop.RemoveOperand(Pop.findRegisterDefOperandIdx(ARM::LR)); + } else if (MBBI->getOpcode() == ARM::tPOP_RET) { + // We couldn't use the direct restoration above, so + // perform the opposite conversion: tPOP_RET to tPOP. + MachineInstrBuilder MIB = + AddDefaultPred( + BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP))); + unsigned Popped = 0; + for (auto MO: MBBI->operands()) + if (MO.isReg() && (MO.isImplicit() || MO.isDef()) && + MO.getReg() != ARM::PC) { + MIB.addOperand(MO); + if (!MO.isImplicit()) + Popped++; + } + // Is there anything left to pop? + if (!Popped) + MBB.erase(MIB.getInstr()); + // Erase the old instruction. + MBB.erase(MBBI); + MBBI = MBB.end(); + AddBx = true; } assert(PopReg && "Do not know how to get LR"); @@ -554,14 +573,20 @@ bool Thumb1FrameLowering::emitPopSpecialFixUp(MachineBasicBlock &MBB, return true; } - AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr)) - .addReg(ARM::LR, RegState::Define) - .addReg(PopReg, RegState::Kill)); - + if (AddBx && !TemporaryReg) { + AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX)) + .addReg(PopReg, RegState::Kill)); + } else { + AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr)) + .addReg(ARM::LR, RegState::Define) + .addReg(PopReg, RegState::Kill)); + } if (TemporaryReg) { AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr)) .addReg(PopReg, RegState::Define) .addReg(TemporaryReg, RegState::Kill)); + if (AddBx) + AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET))); } return true; @@ -628,7 +653,7 @@ restoreCalleeSavedRegisters(MachineBasicBlock &MBB, if (isVarArg) continue; // ARMv4T requires BX, see emitEpilogue - if (STI.hasV4TOps() && !STI.hasV5TOps()) + if (!STI.hasV5TOps()) continue; Reg = ARM::PC; (*MIB).setDesc(TII.get(ARM::tPOP_RET)); diff --git a/test/CodeGen/ARM/debug-frame.ll b/test/CodeGen/ARM/debug-frame.ll index 33d38969899..4bd401b6849 100644 --- a/test/CodeGen/ARM/debug-frame.ll +++ b/test/CodeGen/ARM/debug-frame.ll @@ -30,11 +30,11 @@ ; RUN: -filetype=asm -o - %s \ ; RUN: | FileCheck %s --check-prefix=CHECK-V7-FP-ELIM -; RUN: llc -mtriple thumb-unknown-linux-gnueabi \ +; RUN: llc -mtriple thumbv5-unknown-linux-gnueabi \ ; RUN: -disable-fp-elim -filetype=asm -o - %s \ ; RUN: | FileCheck %s --check-prefix=CHECK-THUMB-FP -; RUN: llc -mtriple thumb-unknown-linux-gnueabi \ +; RUN: llc -mtriple thumbv5-unknown-linux-gnueabi \ ; RUN: -filetype=asm -o - %s \ ; RUN: | FileCheck %s --check-prefix=CHECK-THUMB-FP-ELIM diff --git a/test/CodeGen/Thumb/large-stack.ll b/test/CodeGen/Thumb/large-stack.ll index 0d534589ae0..c5d1044e9d6 100644 --- a/test/CodeGen/Thumb/large-stack.ll +++ b/test/CodeGen/Thumb/large-stack.ll @@ -32,10 +32,10 @@ define void @test100() { ; Smallest stack for which we use a constant pool define void @test2() { ; CHECK-LABEL: test2: -; CHECK: ldr r0, -; CHECK: add sp, r0 -; EABI: ldr r0, -; EABI: add sp, r0 +; CHECK: ldr [[TEMP:r[0-7]]], +; CHECK: add sp, [[TEMP]] +; EABI: ldr [[TEMP:r[0-7]]], +; EABI: add sp, [[TEMP]] ; IOS: subs r4, r7, #4 ; IOS: mov sp, r4 %tmp = alloca [ 1528 x i8 ] , align 4 @@ -44,12 +44,12 @@ define void @test2() { define i32 @test3() { ; CHECK-LABEL: test3: -; CHECK: ldr r1, -; CHECK: add sp, r1 -; CHECK: ldr r1, -; CHECK: add r1, sp -; EABI: ldr r1, -; EABI: add sp, r1 +; CHECK: ldr [[TEMP:r[0-7]]], +; CHECK: add sp, [[TEMP]] +; CHECK: ldr [[TEMP]], +; CHECK: add [[TEMP]], sp +; EABI: ldr [[TEMP:r[0-7]]], +; EABI: add sp, [[TEMP]] ; IOS: subs r4, r7, #4 ; IOS: mov sp, r4 %retval = alloca i32, align 4 diff --git a/test/CodeGen/Thumb/pop-special-fixup.ll b/test/CodeGen/Thumb/pop-special-fixup.ll deleted file mode 100644 index 9ba589d6cec..00000000000 --- a/test/CodeGen/Thumb/pop-special-fixup.ll +++ /dev/null @@ -1,60 +0,0 @@ -; RUN: llc %s -enable-shrink-wrap=true -o - | FileCheck %s - -target triple = "thumbv6m-none-none-eabi" - -@retval = global i32 0, align 4 - -define i32 @test(i32 %i, i32 %argc, i8** nocapture readonly %argv) { - %1 = icmp sgt i32 %argc, %i - br i1 %1, label %2, label %19 - - %3 = getelementptr inbounds i8*, i8** %argv, i32 %i - %4 = load i8*, i8** %3, align 4 - %5 = load i8, i8* %4, align 1 - %6 = icmp eq i8 %5, 45 - %7 = getelementptr inbounds i8, i8* %4, i32 1 - %. = select i1 %6, i8* %7, i8* %4 - %.1 = select i1 %6, i32 -1, i32 1 - %8 = load i8, i8* %., align 1 - %.off2 = add i8 %8, -48 - %9 = icmp ult i8 %.off2, 10 - %.pre = load i32, i32* @retval, align 4 - br i1 %9, label %.lr.ph.preheader, label %.critedge - -.lr.ph.preheader: ; preds = %2 - br label %.lr.ph - -.lr.ph: ; preds = %.lr.ph.preheader, %.lr.ph - %10 = phi i32 [ %14, %.lr.ph ], [ %.pre, %.lr.ph.preheader ] - %11 = phi i8 [ %15, %.lr.ph ], [ %8, %.lr.ph.preheader ] - %valstring.03 = phi i8* [ %13, %.lr.ph ], [ %., %.lr.ph.preheader ] - %12 = zext i8 %11 to i32 - %13 = getelementptr inbounds i8, i8* %valstring.03, i32 1 - %14 = add nsw i32 %10, %12 - store i32 %14, i32* @retval, align 4 - %15 = load i8, i8* %13, align 1 - %.off = add i8 %15, -48 - %16 = icmp ult i8 %.off, 10 - br i1 %16, label %.lr.ph, label %.critedge.loopexit - -.critedge.loopexit: ; preds = %.lr.ph - %.lcssa = phi i32 [ %14, %.lr.ph ] - br label %.critedge - -.critedge: ; preds = %.critedge.loopexit, %2 - %17 = phi i32 [ %.pre, %2 ], [ %.lcssa, %.critedge.loopexit ] - %18 = mul nsw i32 %17, %.1 - store i32 %18, i32* @retval, align 4 - br label %19 - -;