From d1c48227d7c45fbb35c81f846a62ec92a74f4701 Mon Sep 17 00:00:00 2001 From: "Ji-Ze Hong (Peter Hong)" Date: Thu, 11 Jan 2018 14:47:20 +0800 Subject: [PATCH] USB: serial: f81534: fix tx error on some baud rate The F81532/534 had 4 clocksource 1.846/18.46/14.77/24MHz and baud rates can be up to 1.5Mbits with 24MHz. But on some baud rate (384~500kps), the TX side will send the data frame too close to treat frame error on RX side. This patch will force all TX data frame with delay 1bit gap. Signed-off-by: Ji-Ze Hong (Peter Hong) Signed-off-by: Johan Hovold --- drivers/usb/serial/f81534.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/usb/serial/f81534.c b/drivers/usb/serial/f81534.c index 86edec3e8c05..4dfbff20bda4 100644 --- a/drivers/usb/serial/f81534.c +++ b/drivers/usb/serial/f81534.c @@ -131,6 +131,7 @@ #define F81534_CLK_24_MHZ BIT(2) #define F81534_CLK_14_77_MHZ (BIT(1) | BIT(2)) #define F81534_CLK_MASK GENMASK(2, 1) +#define F81534_CLK_TX_DELAY_1BIT BIT(3) #define F81534_CLK_RS485_MODE BIT(4) #define F81534_CLK_RS485_INVERT BIT(5) @@ -1386,7 +1387,11 @@ static int f81534_port_probe(struct usb_serial_port *port) if (!port_priv) return -ENOMEM; - port_priv->shadow_clk = F81534_UART_EN; + /* + * We'll make tx frame error when baud rate from 384~500kps. So we'll + * delay all tx data frame with 1bit. + */ + port_priv->shadow_clk = F81534_UART_EN | F81534_CLK_TX_DELAY_1BIT; spin_lock_init(&port_priv->msr_lock); mutex_init(&port_priv->mcr_mutex); mutex_init(&port_priv->lcr_mutex); -- 2.11.0