From d1dace8aea073716daf0055ad07fde1164b2a472 Mon Sep 17 00:00:00 2001 From: Andrew Trick Date: Fri, 21 Jan 2011 06:19:05 +0000 Subject: [PATCH] Enable support for precise scheduling of the instruction selection DAG. Disable using "-disable-sched-cycles". For ARM, this enables a framework for modeling the cpu pipeline and counting stalls. It also activates several heuristics to drive scheduling based on the model. Scheduling is inherently imprecise at this stage, and until spilling is improved it may defeat attempts to schedule. However, this framework provides greater control over tuning codegen. Although the flag is not target-specific, it should have very little affect on the default scheduler used by x86. The only two changes that affect x86 are: - scheduling a high-latency operation bumps the current cycle so independent operations can have their latency covered. i.e. two independent 4 cycle operations can produce results in 4 cycles, not 8 cycles. - Two operations with equal register pressure impact and no latency-based stalls on their uses will be prioritized by depth before height (height is irrelevant if no stalls occur in the schedule below this point). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123971 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | 2 +- test/CodeGen/ARM/vcgt.ll | 4 ++-- test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll | 13 +++++++++---- 3 files changed, 12 insertions(+), 7 deletions(-) diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index e43bcfdac9b..ad835806a4e 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -67,7 +67,7 @@ static RegisterScheduler createILPListDAGScheduler); static cl::opt DisableSchedCycles( - "disable-sched-cycles", cl::Hidden, cl::init(true), + "disable-sched-cycles", cl::Hidden, cl::init(false), cl::desc("Disable cycle-level precision during preRA scheduling")); namespace { diff --git a/test/CodeGen/ARM/vcgt.ll b/test/CodeGen/ARM/vcgt.ll index 7663da3c612..c3c4cb35630 100644 --- a/test/CodeGen/ARM/vcgt.ll +++ b/test/CodeGen/ARM/vcgt.ll @@ -161,9 +161,9 @@ define <4 x i32> @vacgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind { ; rdar://7923010 define <4 x i32> @vcgt_zext(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK: vcgt_zext: +;CHECK: vmov.i32 q10, #0x1 ;CHECK: vcgt.f32 q8 -;CHECK: vmov.i32 q9, #0x1 -;CHECK: vand q8, q8, q9 +;CHECK: vand q8, q8, q10 %tmp1 = load <4 x float>* %A %tmp2 = load <4 x float>* %B %tmp3 = fcmp ogt <4 x float> %tmp1, %tmp2 diff --git a/test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll b/test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll index 7ee19863de1..458569ec93b 100644 --- a/test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll +++ b/test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll @@ -1,4 +1,7 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 \ +; RUN: -pre-RA-sched=source | FileCheck -check-prefix=SOURCE %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 \ +; RUN: -pre-RA-sched=list-hybrid | FileCheck -check-prefix=HYBRID %s ; Radar 7459078 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" @@ -10,9 +13,11 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32- %s5 = type { i32 } ; Make sure the cmp is not scheduled before the InlineAsm that clobbers cc. -; CHECK: InlineAsm End -; CHECK: cmp -; CHECK: beq +; SOURCE: InlineAsm End +; SOURCE: cmp +; SOURCE: beq +; HYBRID: InlineAsm End +; HYBRID: cbz define void @test(%s1* %this, i32 %format, i32 %w, i32 %h, i32 %levels, i32* %s, i8* %data, i32* nocapture %rowbytes, void (i8*, i8*)* %release, i8* %info) nounwind { entry: %tmp1 = getelementptr inbounds %s1* %this, i32 0, i32 0, i32 0, i32 1, i32 0, i32 0 -- 2.11.0