From d22c564958ffa6bd40be34c6ea3333ee7ef73b68 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Fri, 19 Aug 2022 12:00:50 +0100 Subject: [PATCH] target/arm: Implement ID_DFR1 In Armv8.6, a new AArch32 ID register ID_DFR1 is defined; implement it. We don't have any CPUs with features that they need to advertise here yet, but plumbing in the ID register gives it the right name when debugging and will help in future when we do add a CPU that has non-zero ID_DFR1 fields. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-Id: <20220819110052.2942289-5-peter.maydell@linaro.org> Signed-off-by: Richard Henderson --- target/arm/cpu.h | 1 + target/arm/helper.c | 4 ++-- target/arm/kvm64.c | 2 ++ 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index fcc5927587..fa24ce9f96 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -983,6 +983,7 @@ struct ArchCPU { uint32_t mvfr1; uint32_t mvfr2; uint32_t id_dfr0; + uint32_t id_dfr1; uint32_t dbgdidr; uint32_t dbgdevid; uint32_t dbgdevid1; diff --git a/target/arm/helper.c b/target/arm/helper.c index 0737851925..7ff03f1a4b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7581,11 +7581,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa64_tid3, .resetvalue = cpu->isar.id_pfr2 }, - { .name = "RES_0_C0_C3_5", .state = ARM_CP_STATE_BOTH, + { .name = "ID_DFR1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa64_tid3, - .resetvalue = 0 }, + .resetvalue = cpu->isar.id_dfr1 }, { .name = "ID_MMFR5", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST, diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 2d737c443e..1197253d12 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -643,6 +643,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) ARM64_SYS_REG(3, 0, 0, 3, 2)); err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr2, ARM64_SYS_REG(3, 0, 0, 3, 4)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr1, + ARM64_SYS_REG(3, 0, 0, 3, 5)); err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr5, ARM64_SYS_REG(3, 0, 0, 3, 6)); -- 2.11.0