From d30a079ad346b1f3c61eb275f011542e8886f671 Mon Sep 17 00:00:00 2001 From: "astoria-d@office" Date: Thu, 19 May 2016 13:41:38 +0900 Subject: [PATCH] simulation env setup ok --- de0_cv_nes/.gitignore | 4 + de0_cv_nes/de0_cv_nes.vhd | 7 +- .../simulation/modelsim/de0_cv_nes_modelsim.mpf | 257 ++++++++++++++++ .../modelsim/de0_cv_nes_run_msim_gate_vhdl.do | 17 ++ .../modelsim/de0_cv_nes_run_msim_rtl_vhdl.do | 123 ++++++++ de0_cv_nes/simulation/modelsim/modelsim.ini | 324 +++++++++++++++++++++ de0_cv_nes/testbench_motones_sim.vhd | 184 ++++++++++++ 7 files changed, 911 insertions(+), 5 deletions(-) create mode 100644 de0_cv_nes/simulation/modelsim/de0_cv_nes_modelsim.mpf create mode 100644 de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_gate_vhdl.do create mode 100644 de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do create mode 100644 de0_cv_nes/simulation/modelsim/modelsim.ini create mode 100644 de0_cv_nes/testbench_motones_sim.vhd diff --git a/de0_cv_nes/.gitignore b/de0_cv_nes/.gitignore index b610877..2efbcdc 100644 --- a/de0_cv_nes/.gitignore +++ b/de0_cv_nes/.gitignore @@ -1,5 +1,6 @@ *.bak *.qws +*.rpt output_files/* db/* incremental_db/* @@ -10,9 +11,12 @@ simulation/modelsim/rtl_work/* simulation/modelsim/*.do.bak* simulation/modelsim/msim_transcript simulation/modelsim/*.vho +simulation/modelsim/*.mti simulation/modelsim/*.xrf simulation/modelsim/*.sdo* simulation/modelsim/*.sft +simulation/modelsim/*.mif +simulation/modelsim/*.hex simulation/modelsim/vsim.wlf simulation/modelsim/work/* simulation/modelsim/transcript diff --git a/de0_cv_nes/de0_cv_nes.vhd b/de0_cv_nes/de0_cv_nes.vhd index c5386c4..46ed299 100644 --- a/de0_cv_nes/de0_cv_nes.vhd +++ b/de0_cv_nes/de0_cv_nes.vhd @@ -357,11 +357,8 @@ begin phi1, phi2, addr, d_io); --main ROM/RAM instance --- prg_rom_inst : prg_rom generic map (rom_32k, data_size) --- port map (mem_clk, rom_ce_n, addr(rom_32k - 1 downto 0), d_io); - - prg_rom_inst : prg_rom generic map (rom_8k, data_size) - port map (mem_clk, rom_ce_n, addr(rom_8k - 1 downto 0), d_io); + prg_rom_inst : prg_rom generic map (rom_32k, data_size) + port map (mem_clk, rom_ce_n, addr(rom_32k - 1 downto 0), d_io); ram_oe_n <= not R_nW; prg_ram_inst : ram generic map (ram_2k, data_size) diff --git a/de0_cv_nes/simulation/modelsim/de0_cv_nes_modelsim.mpf b/de0_cv_nes/simulation/modelsim/de0_cv_nes_modelsim.mpf new file mode 100644 index 0000000..828d7bd --- /dev/null +++ b/de0_cv_nes/simulation/modelsim/de0_cv_nes_modelsim.mpf @@ -0,0 +1,257 @@ +[Library] +others = $MODEL_TECH/../modelsim.ini + +; Altera specific primitive library mappings + +work = work +[vcom] +; Turn on VHDL-1993 as the default. Normally is off. +; VHDL93 = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; .ini file has Explict enable so that std_logic_signed/unsigned +; will match synthesis tools behavior. + Explicit = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = false + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off inclusion of debugging info within design units. Default is to include. +; NoDebug = 1 + +; Turn off "loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. + +; RequireConfigForAllDefaultBinding = 1 + +[vlog] + +; Turn off inclusion of debugging info within design units. Default is to include. +; NoDebug = 1 + +; Turn off "loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Turns on incremental compilation of modules +; Incremental = 1 + +[vsim] +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ps + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +UserTimeUnit = default + +; Default run length +RunLength = 100 + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Directive to license manager: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; nomgc Do not look for Mentor Graphics Licenses +; nomti Do not look for Model Technology Licenses +; noqueue Do not wait in the license queue when a license isn't available +; License = plus + +; Stop the simulator after an assertion message +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Assertion Message Format +; %S - Severity Level +; %R - Report Message +; %T - Time of assertion +; %D - Delta +; %I - Instance or Region pathname (if available) +; %% - print '%' character +; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Assertion File - alternate file for storing assertion messages +; AssertFile = assert.log + +; Default radix for all windows and commands... +; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned +DefaultRadix = symbolic + +; VSIM Startup command +; Startup = do startup.do + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +;CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. For VHDL, PathSeparator = / +; for Verilog, PathSeparator = . +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example, sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Disable assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Default force kind. May be freeze, drive, or deposit +; or in other terms, fixed, wired or charged. +; DefaultForceKind = freeze + +; If zero, open files when elaborated +; else open files on first read or write +; DelayFileOpen = 0 + +; Control VHDL files opened for write +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control number of VHDL files open concurrently +; This number should always be less then the +; current ulimit setting for max file descriptors +; 0 = unlimited +ConcurrentFileLimit = 40 + +; This controls the number of hierarchical regions displayed as +; part of a signal name shown in the waveform window. The default +; value or a value of zero tells VSIM to display the full name. +; WaveSignalNameWidth = 0 + +; Turn off warnings from the std_logic_arith, std_logic_unsigned +; and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from the IEEE numeric_std and numeric_bit +; packages. +; NumericStdNoWarnings = 1 + +; Control the format of a generate statement label. Don't quote it. +; GenerateFormat = %s__%d + +; Specify whether checkpoint files should be compressed. +; The default is to be compressed. +; CheckpointCompressMode = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl +[Project] +; Warning -- Do not edit the project properties directly. +; Property names are dynamic in nature and property +; values have special syntax. Changing property data directly +; can result in a corrupt MPF file. All project properties +; can be modified through project window dialogs. +Project_Version = 6 +Project_DefaultLib = work +Project_SortMethod = unused +Project_Files_Count = 0 +Project_Sim_Count = 1 +Project_Sim_0 = Simulation 1 +Project_Sim_P_0 = timing default -t default -sdfnoerror 0 -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder {Top Level} +pulse_e {} additional_dus de0_cv_nes -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {} +Project_Folder_Count = 0 +Echo_Compile_Output = 0 +Save_Compile_Report = 1 +Project_Opt_Count = 0 +ForceSoftPaths = 0 +ProjectStatusDelay = 5000 +VERILOG_DoubleClick = Edit +VERILOG_CustomDoubleClick = +SYSTEMVERILOG_DoubleClick = Edit +SYSTEMVERILOG_CustomDoubleClick = +VHDL_DoubleClick = Edit +VHDL_CustomDoubleClick = +PSL_DoubleClick = Edit +PSL_CustomDoubleClick = +TEXT_DoubleClick = Edit +TEXT_CustomDoubleClick = +SYSTEMC_DoubleClick = Edit +SYSTEMC_CustomDoubleClick = +TCL_DoubleClick = Edit +TCL_CustomDoubleClick = +MACRO_DoubleClick = Edit +MACRO_CustomDoubleClick = +VCD_DoubleClick = Edit +VCD_CustomDoubleClick = +SDF_DoubleClick = Edit +SDF_CustomDoubleClick = +XML_DoubleClick = Edit +XML_CustomDoubleClick = +LOGFILE_DoubleClick = Edit +LOGFILE_CustomDoubleClick = +UCDB_DoubleClick = Edit +UCDB_CustomDoubleClick = +UPF_DoubleClick = Edit +UPF_CustomDoubleClick = +PCF_DoubleClick = Edit +PCF_CustomDoubleClick = +PROJECT_DoubleClick = Edit +PROJECT_CustomDoubleClick = +VRM_DoubleClick = Edit +VRM_CustomDoubleClick = +DEBUGDATABASE_DoubleClick = Edit +DEBUGDATABASE_CustomDoubleClick = +DEBUGARCHIVE_DoubleClick = Edit +DEBUGARCHIVE_CustomDoubleClick = +Project_Major_Version = 10 +Project_Minor_Version = 1 diff --git a/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_gate_vhdl.do b/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_gate_vhdl.do new file mode 100644 index 0000000..4ecc480 --- /dev/null +++ b/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_gate_vhdl.do @@ -0,0 +1,17 @@ +transcript on +if {[file exists gate_work]} { + vdel -lib gate_work -all +} +vlib gate_work +vmap work gate_work + +vcom -93 -work work {de0_cv_nes.vho} + +vcom -93 -work work {C:/Users/motooka/Documents/001-proj/999.my-proj/001.nes-fpga/repo/motonesfpga/de0_cv_nes/testbench_motones_sim.vhd} + +vsim -t 1ps +transport_int_delays +transport_path_delays -sdftyp /NA=de0_cv_nes_vhd.sdo -L altera -L altera_lnsim -L cyclonev -L gate_work -L work -voptargs="+acc" testbench_motones_sim + +add wave * +view structure +view signals +run -all diff --git a/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do b/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do new file mode 100644 index 0000000..4e7d47a --- /dev/null +++ b/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do @@ -0,0 +1,123 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vcom -93 -work work {C:/Users/motooka/Documents/001-proj/999.my-proj/001.nes-fpga/repo/motonesfpga/de1_nes/address_decoder.vhd} +vcom -93 -work work {C:/Users/motooka/Documents/001-proj/999.my-proj/001.nes-fpga/repo/motonesfpga/de1_nes/motonesfpga_common.vhd} +vcom -93 -work work {C:/Users/motooka/Documents/001-proj/999.my-proj/001.nes-fpga/repo/motonesfpga/de1_nes/clock/clock_divider.vhd} +vcom -93 -work work {C:/Users/motooka/Documents/001-proj/999.my-proj/001.nes-fpga/repo/motonesfpga/de1_nes/mem/ram.vhd} +vcom -93 -work work {C:/Users/motooka/Documents/001-proj/999.my-proj/001.nes-fpga/repo/motonesfpga/de1_nes/apu/apu.vhd} +vcom -93 -work work {C:/Users/motooka/Documents/001-proj/999.my-proj/001.nes-fpga/repo/motonesfpga/de1_nes/ppu/ppu_registers.vhd} +vcom -93 -work work {C:/Users/motooka/Documents/001-proj/999.my-proj/001.nes-fpga/repo/motonesfpga/de1_nes/cpu/cpu_registers.vhd} +vcom -93 -work work {C:/Users/motooka/Documents/001-proj/999.my-proj/001.nes-fpga/repo/motonesfpga/de1_nes/cpu/mos6502.vhd} +vcom -93 -work work {C:/Users/motooka/Documents/001-proj/999.my-proj/001.nes-fpga/repo/motonesfpga/de0_cv_nes/de0_cv_nes.vhd} +vcom -93 -work work {C:/Users/motooka/Documents/001-proj/999.my-proj/001.nes-fpga/repo/motonesfpga/de1_nes/mem/chr_rom.vhd} +vcom -93 -work work {C:/Users/motooka/Documents/001-proj/999.my-proj/001.nes-fpga/repo/motonesfpga/de1_nes/ppu/ppu.vhd} +vcom -93 -work work {C:/Users/motooka/Documents/001-proj/999.my-proj/001.nes-fpga/repo/motonesfpga/de1_nes/ppu/vga_ppu.vhd} +vcom -93 -work work {C:/Users/motooka/Documents/001-proj/999.my-proj/001.nes-fpga/repo/motonesfpga/de1_nes/mem/prg_rom.vhd} +vcom -93 -work work {C:/Users/motooka/Documents/001-proj/999.my-proj/001.nes-fpga/repo/motonesfpga/de1_nes/cpu/alu.vhd} +vcom -93 -work work {C:/Users/motooka/Documents/001-proj/999.my-proj/001.nes-fpga/repo/motonesfpga/de1_nes/cpu/decoder.vhd} + +vcom -93 -work work {C:/Users/motooka/Documents/001-proj/999.my-proj/001.nes-fpga/repo/motonesfpga/de0_cv_nes/testbench_motones_sim.vhd} + +vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev -L rtl_work -L work -voptargs="+acc" testbench_motones_sim + +#add wave * +#view structure +#view signals +#run -all + + +##script custom part... + + +add wave -label rst_n sim:/testbench_motones_sim/sim_board/rst_n; +add wave -label r_nw sim:/testbench_motones_sim/sim_board/r_nw; +add wave -label cpu_clk sim:/testbench_motones_sim/sim_board/cpu_clk +add wave -label addr -radix hex sim:/testbench_motones_sim/sim_board/addr +add wave -label d_io -radix hex sim:/testbench_motones_sim/sim_board/d_io + +add wave -label instruction -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/instruction +add wave -label int_d_bus -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/int_d_bus +add wave -label exec_cycle -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/exec_cycle + +add wave -divider regs +add wave -label acc -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/acc/q +add wave -label status_val -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/status_register/status_val +add wave -label sp -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/sp/q +add wave -label x -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/x/q +add wave -label y -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/y/q + + +##add wave -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/status_reg + +add wave -divider ppu +add wave -label cpu_addr -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/cpu_addr +add wave -label cpu_d -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/cpu_d +add wave -label ppu_ce_n sim:/testbench_motones_sim/sim_board/ppu_inst/ce_n +add wave -label ppu_clk sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_clk +add wave -label ppu_clk_cnt -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_clk_cnt +add wave -label ppu_ctl -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_ctrl +add wave -label ppu_mask -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_mask +add wave -label ppu_status -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_status +#add wave -label ppu_addr_cnt -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_cnt +#add wave -label ppu_addr_we_n -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_we_n +#add wave -label ppu_addr_in -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_in +#add wave -label ppu_addr_inc1 -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_inc1 +#add wave -label ppu_addr_inc32 -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_inc32 +add wave -label ppu_addr -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr +add wave -label ppu_data -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_data + + +add wave -divider ppu_scrl +add wave -label ppu_ce_n sim:/testbench_motones_sim/sim_board/ppu_inst/ce_n +add wave -label ppu_clk sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_clk +add wave -label ppu_scroll_cnt -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_cnt + +add wave -label ppu_clk_cnt -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_clk_cnt + +add wave -label ppu_scroll_cnt_ce_n sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_cnt_ce_n +add wave -label ppu_scroll_x_we_n sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_x_we_n +add wave -label ppu_scroll_y_we_n sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_y_we_n +add wave -label ppu_scr_x -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_x +add wave -label ppu_scr_y -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_y + + +#add wave -divider render +# +##add wave -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/pos_x \ +##sim:/testbench_motones_sim/sim_board/ppu_inst/pos_y +# +##add wave -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/nes_r \ +##sim:/testbench_motones_sim/sim_board/ppu_inst/nes_g \ +##sim:/testbench_motones_sim/sim_board/ppu_inst/nes_b +# +#add wave -label h_sync_n sim:/testbench_motones_sim/sim_board/ppu_inst/h_sync_n +#add wave -label v_sync_n sim:/testbench_motones_sim/sim_board/ppu_inst/v_sync_n + + + +#add wave -divider apu +#add wave -label cpu_addr sim:/testbench_motones_sim/sim_board/apu_inst/dma_start_n +#add wave -label dma_next_status -radix hex sim:/testbench_motones_sim/sim_board/apu_inst/dma_next_status +#add wave -label dma_status -radix hex sim:/testbench_motones_sim/sim_board/apu_inst/dma_status +#add wave -label dma_cnt_ce sim:/testbench_motones_sim/sim_board/apu_inst/dma_cnt_ce +#add wave -label rdy sim:/testbench_motones_sim/sim_board/apu_inst/rdy +#add wave -label dma_write_we_n sim:/testbench_motones_sim/sim_board/apu_inst/dma_write_we_n +#add wave -label dma_addr -radix hex sim:/testbench_motones_sim/sim_board/apu_inst/dma_addr +#add wave -label dma_start_n sim:/testbench_motones_sim/sim_board/apu_inst/dma_start_n +#add wave -label dma_end_n sim:/testbench_motones_sim/sim_board/apu_inst/dma_end_n + + + +view structure +view signals + +run 8 us +wave zoom full + +#run 430 us + diff --git a/de0_cv_nes/simulation/modelsim/modelsim.ini b/de0_cv_nes/simulation/modelsim/modelsim.ini new file mode 100644 index 0000000..fbe35ae --- /dev/null +++ b/de0_cv_nes/simulation/modelsim/modelsim.ini @@ -0,0 +1,324 @@ +; Copyright 1991-2009 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +others = $MODEL_TECH/../modelsim.ini + +; Altera Primitive libraries +; +; VHDL Section +; +; +; Verilog Section +; + +work = gate_work +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Default or value of 3 or 2008 for VHDL-2008. +VHDL93 = 2002 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +[vlog] + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Turn on incremental compilation of modules. Default is off. +; Incremental = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +[vsim] +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ps + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 100 + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Directive to license manager: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; nomgc Do not look for Mentor Graphics Licenses +; nomti Do not look for Model Technology Licenses +; noqueue Do not wait in the license queue when a license isn't available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license +; License = plus + +; Stop the simulator after a VHDL/Verilog assertion message +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Assertion Message Format +; %S - Severity Level +; %R - Report Message +; %T - Time of assertion +; %D - Delta +; %I - Instance or Region pathname (if available) +; %% - print '%' character +; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Assertion File - alternate file for storing VHDL/Verilog assertion messages +; AssertFile = assert.log + +; Default radix for all windows and commands... +; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned +DefaultRadix = symbolic + +; VSIM Startup command +; Startup = do startup.do + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example, sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings from the std_logic_arith, std_logic_unsigned +; and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from the IEEE numeric_std and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Control the format of the (VHDL) FOR generate statement label +; for each iteration. Do not quote it. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate_label; the %d represents the generate parameter value +; at a particular generate iteration (this is the position number if +; the generate parameter is of an enumeration type). Embedded whitespace +; is allowed (but discouraged); leading and trailing whitespace is ignored. +; Application of the format must result in a unique scope name over all +; such names in the design so that name lookup can function properly. +; GenerateFormat = %s__%d + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave +; DefaultRestartOptions = -force + +; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs +; (> 500 megabyte memory footprint). Default is disabled. +; Specify number of megabytes to lock. +; LockedMemory = 1000 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Automatic SDF compilation +; Disables automatic compilation of SDF files in flows that support it. +; Default is on, uncomment to turn off. +; NoAutoSDFCompile = 1 + +[lmc] + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; Examples: +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3043 +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of elaboration/runtime messages. +; The default is to have messages appear in the transcript and +; recorded in the wlf file (messages that are recorded in the +; wlf file can be viewed in the MsgViewer). The other settings +; are to send messages only to the transcript or only to the +; wlf file. The valid values are +; both {default} +; tran {transcript only} +; wlf {wlf file only} +; msgmode = both diff --git a/de0_cv_nes/testbench_motones_sim.vhd b/de0_cv_nes/testbench_motones_sim.vhd new file mode 100644 index 0000000..d9fe9f4 --- /dev/null +++ b/de0_cv_nes/testbench_motones_sim.vhd @@ -0,0 +1,184 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity testbench_motones_sim is +end testbench_motones_sim; + +architecture stimulus of testbench_motones_sim is + component de0_cv_nes + port ( +--debug signal + signal dbg_cpu_clk : out std_logic; + signal dbg_ppu_clk : out std_logic; + signal dbg_mem_clk : out std_logic; + signal dbg_r_nw : out std_logic; + signal dbg_addr : out std_logic_vector( 16 - 1 downto 0); + signal dbg_d_io : out std_logic_vector( 8 - 1 downto 0); + signal dbg_vram_ad : out std_logic_vector (7 downto 0); + signal dbg_vram_a : out std_logic_vector (13 downto 8); + +---monitor inside cpu + signal dbg_instruction : out std_logic_vector(7 downto 0); + signal dbg_int_d_bus : out std_logic_vector(7 downto 0); + signal dbg_exec_cycle : out std_logic_vector (5 downto 0); + signal dbg_ea_carry : out std_logic; + signal dbg_status : out std_logic_vector(7 downto 0); + signal dbg_sp, dbg_x, dbg_y, dbg_acc : out std_logic_vector(7 downto 0); + signal dbg_dec_oe_n : out std_logic; + +--ppu debug pins + signal dbg_ppu_ce_n : out std_logic; + signal dbg_ppu_ctrl, dbg_ppu_mask, dbg_ppu_status : out std_logic_vector (7 downto 0); + signal dbg_ppu_addr : out std_logic_vector (13 downto 0); + signal dbg_ppu_data, dbg_ppu_scrl_x, dbg_ppu_scrl_y : out std_logic_vector (7 downto 0); + signal dbg_disp_nt, dbg_disp_attr : out std_logic_vector (7 downto 0); + signal dbg_nmi : out std_logic; + + +--NES instance + base_clk : in std_logic; + rst_n : in std_logic; + joypad1 : in std_logic_vector(7 downto 0); + joypad2 : in std_logic_vector(7 downto 0); + h_sync_n : out std_logic; + v_sync_n : out std_logic; + r : out std_logic_vector(3 downto 0); + g : out std_logic_vector(3 downto 0); + b : out std_logic_vector(3 downto 0) + ); + end component; + + constant powerup_time : time := 2 us; + constant reset_time : time := 890 ns; + + ---clock frequency = 21,477,270 (21 MHz) + --constant base_clock_time : time := 46 ns; + + --DE1 base clock = 50 MHz + constant base_clock_time : time := 20 ns; + +--debug signal + signal dbg_cpu_clk : std_logic; + signal dbg_ppu_clk : std_logic; + signal dbg_mem_clk : std_logic; + signal dbg_r_nw : std_logic; + signal dbg_addr : std_logic_vector( 16 - 1 downto 0); + signal dbg_d_io : std_logic_vector( 8 - 1 downto 0); + signal dbg_vram_ad : std_logic_vector (7 downto 0); + signal dbg_vram_a : std_logic_vector (13 downto 8); + +---monitor inside cpu + signal dbg_instruction : std_logic_vector(7 downto 0); + signal dbg_int_d_bus : std_logic_vector(7 downto 0); + signal dbg_exec_cycle : std_logic_vector (5 downto 0); + signal dbg_ea_carry : std_logic; + signal dbg_status : std_logic_vector(7 downto 0); + signal dbg_sp, dbg_x, dbg_y, dbg_acc : std_logic_vector(7 downto 0); + signal dbg_dec_oe_n : std_logic; + +--ppu debug pins + signal dbg_ppu_ce_n : std_logic; + signal dbg_ppu_ctrl, dbg_ppu_mask, dbg_ppu_status : std_logic_vector (7 downto 0); + signal dbg_ppu_addr : std_logic_vector (13 downto 0); + signal dbg_ppu_data, dbg_ppu_scrl_x, dbg_ppu_scrl_y : std_logic_vector (7 downto 0); + signal dbg_disp_nt, dbg_disp_attr : std_logic_vector (7 downto 0); + signal dbg_nmi : std_logic; + + +--NES instance + signal base_clk : std_logic; + signal rst_n : std_logic; + signal joypad1 : std_logic_vector(7 downto 0); + signal joypad2 : std_logic_vector(7 downto 0); + signal h_sync_n : std_logic; + signal v_sync_n : std_logic; + signal r : std_logic_vector(3 downto 0); + signal g : std_logic_vector(3 downto 0); + signal b : std_logic_vector(3 downto 0); +begin + + sim_board : de0_cv_nes port map ( +--debug signal + dbg_cpu_clk , + dbg_ppu_clk , + dbg_mem_clk , + dbg_r_nw , + dbg_addr , + dbg_d_io , + dbg_vram_ad , + dbg_vram_a , + +---monitor inside cpu + dbg_instruction , + dbg_int_d_bus , + dbg_exec_cycle , + dbg_ea_carry , + dbg_status , + dbg_sp, dbg_x, dbg_y, dbg_acc , + dbg_dec_oe_n , + +--ppu debug pins + dbg_ppu_ce_n , + dbg_ppu_ctrl, dbg_ppu_mask, dbg_ppu_status , + dbg_ppu_addr , + dbg_ppu_data, dbg_ppu_scrl_x, dbg_ppu_scrl_y , + dbg_disp_nt, dbg_disp_attr , + dbg_nmi , + + +--NES instance + base_clk , + rst_n , + joypad1 , + joypad2 , + h_sync_n , + v_sync_n , + r , + g , + b +); + + --- input reset. + reset_p: process + begin + rst_n <= '1'; + wait for powerup_time; + + rst_n <= '0'; + wait for reset_time; + + rst_n <= '1'; + wait; + end process; + + --- generate base clock. + clock_p: process + begin + base_clk <= '1'; + wait for base_clock_time / 2; + base_clk <= '0'; + wait for base_clock_time / 2; + end process; + +-- --- initiate nmi. +-- nmi_p: process +-- constant nmi_wait : time := 100 us; +-- constant vblank_time : time := 60 us; +-- variable wait_cnt : integer := 0; +-- begin +-- +-- if (wait_cnt = 0) then +-- nmi_input <= '1'; +-- wait for powerup_time + reset_time + nmi_wait; +-- wait_cnt := wait_cnt + 1; +-- else +-- nmi_input <= '0'; +-- wait for vblank_time ; +-- nmi_input <= '1'; +-- wait for vblank_time / 4; +-- end if; +-- end process; + +end stimulus; + -- 2.11.0