From d31305af4f01e887dbd8b1749106f7da2ede3015 Mon Sep 17 00:00:00 2001 From: Tony Tye Date: Tue, 27 Mar 2018 21:20:46 +0000 Subject: [PATCH] [AMDGPU] Define code object identification string used in AMDHSA runtimes. Differential Revision: https://reviews.llvm.org/D44718 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328669 91177308-0d34-0410-b5e6-96231b3b80d8 --- docs/AMDGPUUsage.rst | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/docs/AMDGPUUsage.rst b/docs/AMDGPUUsage.rst index 0bf9b98d32b..3076332661a 100644 --- a/docs/AMDGPUUsage.rst +++ b/docs/AMDGPUUsage.rst @@ -910,6 +910,34 @@ This section provides code conventions used when the target triple OS is .. _amdgpu-amdhsa-hsa-code-object-metadata: +Code Object Target Identification +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The AMDHSA OS uses the following syntax to specify the code object +target as a single string: + + ``----`` + +Where: + + - ````, ````, ```` and ```` + are the same as the *Target Triple* (see + :ref:`amdgpu-target-triples`). + + - ```` is the same as the *Processor* (see + :ref:`amdgpu-processors`). + + - ```` is a list of the enabled *Target Features* + (see :ref:`amdgpu-target-features`), each prefixed by a plus, that + apply to *Processor*. The list must be in the same order as listed + in the table :ref:`amdgpu-target-feature-table`. Note that *Target + Features* must be included in the list if they are enabled even if + that is the default for *Processor*. + +For example: + + ``"amdgcn-amd-amdhsa--gfx902+xnack"`` + Code Object Metadata ~~~~~~~~~~~~~~~~~~~~ -- 2.11.0